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cynse70064 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-02041 rev. ** revised january 17, 2002 cynse70064 network search engine
cynse70064 document #: 38-02041 rev. ** page 2 of 124 contents 1.0 features ................................................................................................................. .................... 9 2.0 functional overview ...................................................................................................... ....... 9 3.0 product summary .......................................................................................................... ....... 10 3.1 logic block diagram ...................................................................................................... ............. 10 4.0 functional description ................................................................................................... ... 10 4.1 cmd bus and dq bus ....................................................................................................... .......... 10 4.2 database entry (data array and mask array) ........................................................................... 10 4.3 arbitration logic ........................................................................................................ .................. 10 4.4 pipeline and sram control ................................................................................................ ........ 11 4.5 full logic ............................................................................................................... ....................... 11 5.0 signal descriptions ...................................................................................................... ....... 11 6.0 clocks ................................................................................................................... ..................... 13 7.0 registers ................................................................................................................ .................. 13 7.1 comparand registers ...................................................................................................... ........... 13 7.2 mask registers ........................................................................................................... ................. 14 7.3 search successful registers (ssr[0:7]) ................................................................................... 14 7.4 command register ......................................................................................................... ............. 14 7.5 information register ..................................................................................................... ............... 15 7.6 read burst address register .............................................................................................. ....... 16 7.7 write burst address register description ................................................................................ 1 6 7.8 nfa register ............................................................................................................. ................... 16 8.0 nse architecture and operation overview .............................................................. 17 9.0 data and mask addressing ............................................................................................... 18 10.0 commands ................................................................................................................ ............... 18 10.1 command codes ........................................................................................................... ............ 18 10.2 commands and command parameters ................................................................................... 19 10.3 read command ............................................................................................................ ............. 19 10.4 write command ........................................................................................................... .............. 22 10.5 search command .......................................................................................................... ............24 10.6 68-bit search on tables configured as 68 using a single cynse70064 device ............... 24 10.7 68-bit search on tables configured as 68 using up to eight cynse70064 devices ....... 26 10.8 68-bit search on tables configured as 68 using up to 31 cynse70064 devices ............ 33 10.9 136-bit search on tables configured as 136 using a single cynse70064 device .......... 48 10.10 136-bit search on tables configured as 136 using up to eight cynse70064 devices . 50 10.11 136-bit search on tables configured as 136 using up to 31 cynse70064 devices ..... 56 10.12 272-bit search on tables configured as ?272 using a single cynse70064 device ........ 71 10.13 272-bit search on tables x272-configured using up to eight cynse70064 devices ....... 73 10.14 272-bit search on tables configured as 272 using up to 31 cynse70064 devices ..... 78 10.15 mixed-sized searches on tables configured with different widths using an cynse70064 device ..................................................................................................... ...... 93 10.16 lram and ldev description .............................................................................................. .... 95 10.17 learn command .......................................................................................................... ............95
cynse70064 document #: 38-02041 rev. ** page 3 of 124 contents (continued) 11.0 depth-cascading ......................................................................................................... ......... 99 11.1 depth-cascading up to eight devices (one block) ................................................................ 99 11.2 depth-cascading up to 31 devices (four blocks) ................................................................ 100 11.3 depth-cascading for a full signal ...................................................................................... 1 00 12.0 sram addressing ......................................................................................................... ...... 101 12.1 generating an sram bus address ....................................................................................... 102 12.2 sram pio access ......................................................................................................... ..........102 12.3 sram read with a table of one device ................................................................................ 102 12.4 sram read with a table of up to eight devices .................................................................. 103 12.5 sram read with a table of up to 31 devices ....................................................................... 106 12.6 sram write with a table of one device ................................................................................ 109 12.7 sram write with a table of up to eight devices .................................................................. 110 12.8 sram write with table(s) of up to 31 devices ..................................................................... 113 13.0 application ............................................................................................................. ............. 116 14.0 jtag (1149.1) testing ................................................................................................... ....... 117 15.0 electrical specifications ............................................................................................. 11 8 16.0 ac timing wave forms .................................................................................................... .. 119 17.0 pinout descriptions and package diagrams ......................................................... 122 18.0 ordering information .................................................................................................... . 122 19.0 package diagrams ........................................................................................................ .... 123
cynse70064 document #: 38-02041 rev. ** page 4 of 124 list of figures figure 6-1. cynse70064 clocks (clk2x and phs_l) ................................................................... 13 figure 7-1. comparand-register selection during search and learn instructions .................... 13 figure 7-2. addressing the global masks register array ............................................................. 14 figure 8-1. cynse70064 database width configuration ............................................................. 17 figure 8-2. multiwidth database configurations example ............................................................ 18 figure 9-1. addressing of the cynse70064 data and mask arrays ............................................. 18 figure 10-1. single-location read cycle timing ........................................................................... 20 figure 10-2. burst read of the data and mask arrays (blen = 4) ................................................ 21 figure 10-3. single write cycle timing ....................................................................................... .... 22 figure 10-4. burst write of the data and mask arrays (blen = 4) ................................................ 23 figure 10-5. timing diagram for 68-bit search in x 68 table (one device) .................................. 25 figure 10-6. timing diagram for 68-bit search in x 68 table (one device) ................................... 25 figure 10-7. 68 table with one device .......................................................................................... 26 figure 10-8. hardware diagram for a table with eight devices ................................................... 28 figure 10-9. timing diagram for 68-bit search device number 0 ................................................. 29 figure 10-10. timing diagram for 68-bit search device number 1 ............................................... 30 figure 10-11. timing diagram for 68-bit search device number 7 (last device) ....................... 31 figure 10-12. x68 table with eight devices ................................................................................... .32 figure 10-13. hardware diagram for a table with 31 devices ....................................................... 34 figure 10-14. hardware diagram for a block of up to eight devices ........................................... 35 figure 10-15. timing diagram for each device in block number 0 (miss on each device) ....... 36 figure 10-16. timing diagram for each device above the winning device in block number 1 37 figure 10-17. timing diagram for globally winning device in block number 1 ......................... 38 figure 10-18. timing diagram for devices below the winning device in block number 1 ........ 39 figure 10-19. timing diagram for devices above the winning device in block number 2 ....... 40 figure 10-20. timing diagram for globally winning device in block number 2 ......................... 41 figure 10-21. timing diagram for devices below the winning device in block number 2 ........ 42 figure 10-22. timing diagram for devices above the winning device in block number 3 ....... 43 figure 10-23. timing diagram for globally winning device in block number 3 ......................... 44 figure 10-24. timing diagram for devices below the winning device in block number 3 (except the last device [device 30]) .......................................................................................... ...... 45 figure 10-25. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table) ............................................................................................ ... 46 figure 10-26. 68 table with 31 devices .......................................................................................... 47 figure 10-27. timing diagram for 136-bit search (one device) .................................................... 48 figure 10-28. hardware diagram for a table with one device ...................................................... 48 figure 10-29. 136 table with one device ....................................................................................... 49 figure 10-30. hardware diagram for a table with eight devices .................................................. 51 figure 10-31. timing diagram for 136-bit search device number 0 ............................................. 52 figure 10-32. timing diagram for 136-bit search device number 1 ............................................. 53 figure 10-33. timing diagram for 136-bit search device number 7 (last device) ..................... 54 figure 10-34. 136 table with eight devices .................................................................................. 55 figure 10-35. hardware diagram for a table with 31 devices ....................................................... 57 figure 10-36. hardware diagram for a block of up to eight devices ........................................... 58 figure 10-37. timing diagram for each device in block number 0 (miss on each device) ....... 59 figure 10-38. timing diagram for each device above the winning device in block number 1 60 figure 10-39. timing diagram for globally winning device in block number 1 ......................... 61 figure 10-40. timing diagram for devices below the winning device in block number 1 ........ 62
cynse70064 document #: 38-02041 rev. ** page 5 of 124 list of figures (continued) figure 10-41. timing diagram for devices above the winning device in block number 2 ....... 63 figure 10-42. timing diagram for globally winning device in block number 2 ......................... 64 figure 10-43. timing diagram for devices below the winning device in block number 2 ........ 65 figure 10-44. timing diagram for devices above the winning device in block number 3 ....... 66 figure 10-45. timing diagram for globally winning device in block number 3 ......................... 67 figure 10-46. timing diagram for devices below the winning device in block number 3 except device 30 (the last device) ............................................................................................ ....... 68 figure 10-47. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table) ............................................................................................ ... 69 figure 10-48. 136 table with 31 devices ....................................................................................... 70 figure 10-49. timing diagram for 272-bit search (one device) .................................................... 71 figure 10-50. hardware diagram for a table with one device ...................................................... 71 figure 10-51. 272 table with one device ...................................................................................... 72 figure 10-52. hardware diagram for a table with eight devices .................................................. 74 figure 10-53. timing diagram for 272-bit search device number 0 ............................................. 75 figure 10-54. timing diagram for 272-bit search device number 1 ............................................. 76 figure 10-55. timing diagram for 272-bit search device number 7 (last device) ..................... 77 figure 10-56. 272 table with eight devices .................................................................................. 78 figure 10-57. hardware diagram for a table with 31 devices ....................................................... 80 figure 10-58. hardware diagram for a block of up to eight devices ........................................... 81 figure 10-59. timing diagram for each device in block number 0 (miss on each device) ....... 82 figure 10-60. timing diagram for each device above the winning device in block number 1 83 figure 10-61. timing diagram for globally winning device in block number 1 ......................... 84 figure 10-62. timing diagram for devices below the winning device in block number 1 ........ 85 figure 10-63. timing diagram for devices above the winning device in block number 2 ....... 86 figure 10-64. timing diagram for globally winning device in block number 2 ......................... 87 figure 10-65. timing diagram for devices below the winning device in block number 2 ........ 88 figure 10-66. timing diagram for devices above the winning device in block number 3 ....... 89 figure 10-67. timing diagram for globally winning device in block number 3 ......................... 90 figure 10-68. timing diagram for devices below the winning device in block number 3 except device 30 (the last device) ............................................................................................ ....... 91 figure 10-69. timing diagram of the last device in block number 3 (device 30 in the table) . 92 figure 10-70. 272 table with 31 devices ....................................................................................... 93 figure 10-71. timing diagram for mixed search (one device) ..................................................... 94 figure 10-72. multiwidth configurations example ......................................................................... 94 figure 10-73. timing diagram of learn (tlsz = 00) ....................................................................... 96 figure 10-74. timing diagram of learn (except on the last device [tlsz = 01]) ....................... 97 figure 10-75. timing diagram of learn on device number 7 (tlsz = 01) ................................... 98 figure 11-1. depth-cascading to form a single block .................................................................. 99 figure 11-2. depth-cascading four blocks .................................................................................. 100 figure 11-3. full generation in a cascaded table ........................................................................ 101 figure 12-1. sram read access (tlsz = 00, hlat = 000, lram = 1, ldev = 1) ..................... 103 figure 12-2. table of a block of eight devices ............................................................................. 10 4 figure 12-3. sram read through device number 0 in a block of eight devices .................... 105 figure 12-4. sram read timing for device number 7 in a block of eight devices ................. 106 figure 12-5. table of 31 devices made of four blocks ................................................................ 107 figure 12-6. sram read through device number 0 in a bank of 31 devices (device number 0 timing) ...................................................................................................... ......... 108
cynse70064 document #: 38-02041 rev. ** page 6 of 124 list of figures (continued) figure 12-7. sram read through device number 0 in bank of 31 devices (device number 30 timing) ..................................................................................................... ........ 109 figure 12-8. sram write access (tlsz = 00, hlat = 000, lram = 1, ldev = 1) ..................... 110 figure 12-9. table of a block of eight devices ............................................................................. 11 1 figure 12-10. sram write through device number 0 in a block of eight devices .................. 112 figure 12-11. sram write timing for device number 7 in block of eight devices .................. 113 figure 12-12. table of 31 devices (four blocks) .......................................................................... 114 figure 12-13. sram write through device number 0 in bank of 31 devices (device 0 timing) ............................................................................................................. ................. 115 figure 12-14. sram write through device number 0 in bank of 31 cynse70064 devices (device number 30 timing) ..................................................................................................... ........ 116 figure 13-1. sample switch/router using the cynse70064 device .......................................... 117 figure 16-1. input wave form for cynse70064 ........................................................................... 119 figure 16-2. output load for cynse70064 ................................................................................... 120 figure 16-3. 2.5 i/o output load equivalent for cynse70064 .................................................... 120 figure 16-4. ac timing wave forms with clk2x ........................................................................ 121 figure 17-1. pinout diagram .................................................................................................. ......... 122 figure 19-1. package ......................................................................................................... .............. 123
cynse70064 document #: 38-02041 rev. ** page 7 of 124 list of tables table 5-1. cynse70064 signal description ................................................................................... 1 1 table 7-1. register overview ................................................................................................. ........... 13 table 7-2. search successful register description ....................................................................... 14 table 7-3. command register description ..................................................................................... 1 4 table 7-4. information register description .................................................................................. .15 table 7-5. read burst register description ................................................................................... .16 table 7-6. write burst register description .................................................................................. .. 16 table 7-7. nfa register ...................................................................................................... .............. 16 table 8-1. bit position match ................................................................................................ ............ 17 table 10-1. command codes .................................................................................................... ........ 18 table 10-2. command parameters ............................................................................................... .... 19 table 10-3. read command parameters ......................................................................................... 1 9 table 10-4. read address format for data array, mask array, or sram .................................... 20 table 10-5. read address format for internal registers ............................................................... 21 table 10-6. read address format for data and mask arrays ....................................................... 21 table 10-7. write address format for data array, mask array, or sram (single write) ............ 22 table 10-8. write address format for internal registers .............................................................. 23 table 10-9. write address format for data and mask array (burst write) .................................. 24 table 10-10. the latency of search from instruction to sram access cycle ............................ 26 table 10-11. shift of ssf and ssv from sadr ............................................................................... 26 table 10-12. hit/miss assumption ............................................................................................. ....... 27 table 10-13. the latency of search from instruction to sram access cycle ............................ 32 table 10-14. shift of ssf and ssv from sadr ............................................................................... 32 table 10-15. hit/miss assumptions ............................................................................................ ...... 33 table 10-16. the latency of search from instruction to sram access cycle ............................ 47 table 10-17. shift of ssf and ssv from sadr ............................................................................... 47 table 10-18. the latency of search from instruction to sram access cycle ............................ 49 table 10-19. shift of ssf and ssv from sadr ............................................................................... 49 table 10-20. hit/miss assumption ............................................................................................. ....... 50 table 10-21. search latency from instruction to sram access cycle ........................................ 55 table 10-22. shift of ssf and ssv from sadr ............................................................................... 55 table 10-23. hit/miss assumption ............................................................................................. ....... 56 table 10-24. the latency of search from instruction to sram access cycle ............................ 70 table 10-25. shift of ssf and ssv from sadr ............................................................................... 70 table 10-26. the latency of search from c and d cycles to sram access cycle .................... 72 table 10-27. shift of ssf and ssv from sadr ............................................................................... 72 table 10-28. hit/miss assumption ............................................................................................. ....... 73 table 10-29. the latency of search from c and d cycles to sram access cycle ..................... 78 table 10-30. shift of ssf and ssv from sadr ............................................................................... 78 table 10-31. hit/miss assumption ............................................................................................. ....... 79 table 10-32. the latency of search from c and d cycles to sram access cycle ..................... 93 table 10-33. shift of ssf and ssv from sadr ............................................................................... 93 table 10-34. the latency of sram write cycle from second cycle of learn instruction ......... 98 table 12-1. sram bus address ................................................................................................. .... 102 table 14-1. supported operations ............................................................................................. .... 117 table 14-2. tap device id register .......................................................................................... ....117 table 15-1. dc electrical characteristics for cynse70064 ......................................................... 118 table 15-2. operating conditions for cynse70064 ..................................................................... 118
cynse70064 document #: 38-02041 rev. ** page 8 of 124 list of tables (continued) table 16-1. ac timing parameters with clk2x ............................................................................ 119 table 16-2. 2.5v ac table for test condition of cynse70064 ................................................... 119 table 18-1. ordering information ............................................................................................. ...... 122
cynse70064 document #: 38-02041 rev. ** page 9 of 124 1.0 features 64k 34-bit entries in a single device 32k entries in 68-bit mode, 16k entries in 136-bit mode, 8k entries in 272-bit mode 66 million transactions per second in 68- and 136-bit configurations 33 million transactions in 34- and 272-bit configurations searches any subfield in a single cycle synchronous pipelined operation up to 31 search engines can be cascaded when cascaded, the database entries can range up to 1984k 34-bit entries multiple width tables in a single database bank glueless interface to industry-standard srams and/or ssrams simple hardware instruction interface ieee 1149.1 test access port 1.8v core voltage supply 2.5/3.3v i/o voltage supply 272-pin bga package . 2.0 functional overview cypress semiconductor corporation ? s (cypress ? s) cynse70064 network search engine (nse) incorporates patent-pending associative processing technology ? (apt) and is designed to be a high-performance, pipelined, synchronous, 32k-entry nse. the cynse70064 database entry size can be 68 bits, 136 bits, or 272 bits. in the 68-bit entry mode, the size of the database is 32k entries. in the 136-bit mode, the size of the database is 16k entries, and in the 272-bit mode, the size of the database is 8k entries. the cynse70064 is configurable to support multiple databases with different entry sizes. the 34-bit entry table can be implemented using the global mask registers (gmrs) building-database size of 64k entries with a single device. the nse can sustain 66 million transactions per second when the database is programmed or configured as 68 or 136 bits. when the database is programmed to have an entry size of 34 or 272 bits, the nse will perform at 33 million transactions per second. the cynse70064 device can be used to accelerate network protocols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. this high-speed, high-capacity nse can be deployed in a variety of networking and communications applications. the perfor- mance and features of the cynse70064 make it attractive in applications such as enterprise lan switches and routers and broadband switching and/or routing equipment supporting multiple data rates at oc ? 48 and beyond. the nse is designed to be scalable in order to support network database sizes to 1984k entries specifically for environments that require large network policy databases.
cynse70064 document #: 38-02041 rev. ** page 10 of 124 3.0 product summary 3.1 logic block diagram 4.0 functional description the following subsections contain command (cmd) and dq bus (command and databus), database entry, arbitration logic, pipeline and sram control, and full logic descriptions. 4.1 cmd bus and dq bus cmd[8:0] carries the cmd and its associated parameter. dq[67:0] is used for data transfer to and from the database entries, which comprise a data and a mask field that are organized as data and mask arrays. the dq bus carries the search data (of the data and mask arrays and internal registers) during the search command as well as the address and data during read and/or write operations. the dq bus can also carry the address information for the flow-through accesses to the external srams and/or ssrams. 4.2 database entry (data array and mask array) each database entry comprises a data and a mask field. the resultant value of the entry is ? 1, ? ? 0, ? or ? x (don ? t care), ? depending on the value in the data and mask bits. the on-chip priority encoder selects the first matching entry in the database that is n earest to location 0. 4.3 arbitration logic when multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines simultaneously in the cascaded system. if multiple matches occur within the cascaded devices, arbitration logic on the search engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive t he sram bus. compare/pio data address decode match logic compare/pio data dq[67:0] cmdv cmd[8:0] lhi[6:0] command and pio access priority encode cmd arbitration logic lho[1:0] pipeline and sram control sadr[21:0] oe_l bho[2:0] ssf we_l ce_l id[4:0] bhi[2:0] ssv ack tap tap controller ale_l fulo[1:0] fuli[6:0] eot full logic full rst_l phs_l decode comparand register pairs [15:0] global mask register pairs [7:0] information and command register burst read register burst write register next-free address register search successful index registers [7:0] clk2x [all registers are 68 bits wide.] configurable as 32k 68 16k 136 8k 272 mask array configurable as 32k 68 16k 136 8k 272 data array
cynse70064 document #: 38-02041 rev. ** page 11 of 124 4.4 pipeline and sram control pipeline latency is added to give enough time to a cascaded system ? s arbitration logic to determine the device that will drive the index of the matching entry on the sram bus. pipeline logic adds latency to both the sram access cycles and the ssf and ssv signals to align them to the host asic receiving the associated data. 4.5 full logic bit[0] in each of the 68-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entri es have bit[0] = 1, the database asserts the full flag, indicating that all the search engines in the depth-cascaded array are ful l. 5.0 signal descriptions table 5-1 lists and describes all cynse70064 signals. table 5-1. cynse70064 signal description symbol type [1] description clocks and reset clk2x i master clock . cynse70064 samples all the data and control pins on the positive edge of clk2x. all signals are driven out of the device on the rising edge of clk2x (when phs_l is low). phs_l i phase . this signal runs at half the frequency of clk2x and generates an internal clk [2] from clk2x. see section 6.0, ? clocks ? on page 13. test i test input (for cypress semiconductor use only) . this signal should be connected to ground. rst_l i reset . driving rst_l low initializes the device to a known state. cmd and dq bus cmd[8:0] i cmd bus . [1:0] specifies the command and [8:2] contains the cmd parameters. the descrip- tions of individual commands explains the details of the parameters. the encoding of commands based on the [1:0] field are: 00: pio read 01: pio write 10: search 11: learn. cmdv i cmd valid . this signal qualifies the cmd bus: 0: no command 1: command. dq[67:0] i/o address/data bus . this signal carries the read and write address and data during register, data, and mask array operations. it carries the compare data during search operations. it also carries the sram address during sram pio accesses. ack [3] t read acknowledge . this signal indicates that valid data is available on the dq bus during register, data, and mask array read operations, or that the data is available on the sram data bus during sram read operations. eot [3] t end of transfer . this signal indicates the end of burst transfer to the data or mask array during read or write burst operations. ssf t search successful flag . when asserted, this signal indicates that the device is the global winner in a search operation. ssv t search successful flag valid . when asserted, this signal qualifies the ssf signal. sram interface sadr[21:0] t sram address . this bus contains address lines to access off-chip srams that contain associative data. see table 12-1 for the details of the generated sram address. in a database of multiple cynse70064s, each corresponding bit of sadr from all cascaded devices must be connected. ce_l t sram chip enable . this is the chip-enable control for external srams. in a database of multiple cynse70064s, ce_l of all cascaded devices must be connected. this signal is then driven by only one of the devices.
cynse70064 document #: 38-02041 rev. ** page 12 of 124 we_l t sram write enable . this is the write-enable control for external srams. in a database of multiple cynse70064s, we_l of all cascaded devices must be connected together. this signal is then driven by only one of the devices. oe_l t sram output enable . this is the output-enable control for external srams. only the last device drives this signal (with the lram bit set). ale_l t address latch enable . when this signal is low, the addresses are valid on the sram address bus. in a database of multiple cynse70064s, the ale_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. cascade interface lhi[6:0] i local hit in . these pins depth-cascade the device to form a larger table. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. all unused lhi pins are connected to a logic 0. (for more information, see section 11.0, ? depth-cascading ? on page 99.) lho[1:0] o local hit out . lho[1] and lho[0] are the same logical signal. either the lho[1] or the lho[0] is connected to one input of the lhi bus of up to four downstream devices in a block of up to eight. (for more information see section 11.0, ? depth-cascading ? on page 99.) bhi[2:0] i block hit in . inputs from the previous block bho[2:0] are tied to bhi[2:0] of the current device. in a four-block system, the last block can contain only seven devices because the identification code 11111 is used for broadcast access. bho[2:0] o block hit out . these outputs from the last device in a block are connected to the bhi[2:0] inputs of the devices in the downstream blocks. fuli[6:0] i full in . each signal in this bus is connected to fulo[0] or fulo[1] of an upstream device to generate the full flag for the depth-cascaded block. fulo[1:0] o full out . fulo[1] and fulo[0] are the same logical signal. one of these two signals must be connected to the fuli of up to four downstream devices in a depth-cascaded table. bit [0] in the data array indicates whether the entry is full (1) or empty (0).this signal is asserted if all bits in the data array are ones. (refer to section 11.0, ? depth-cascading ? on page 99, for information on how to generate the full flag.) full o full flag . when asserted, this signal indicates that the table of multiple depth-cascaded devices is full. device identification id[4:0] i device identification . the binary-encoded device identification for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast address that selects all cascaded search engines in the system. on a broadcast read-only, the device with the ldev bit set to 1 responds. supplies v dd n/a chip core supply . 1.8v. v ddq n/a chip i/o supply . 2.5v or 3.3v. test access port tdi i test access port ? s test data in. tck i test access port ? s test clock. tdo t test access port ? s test data out. tms i test access port ? s test mode select. trst_l i test access port ? s reset. notes: 1. i = input only, i/o = input or output, o = output only, t = three-state output. 2. clk ? is an internal clock signal. any reference to ? clk cycles ? means one cycle of clk. 3. ack and eot require a weak external pulldown such as 47k ? or 100k ? . table 5-1. cynse70064 signal description (continued) symbol type [1] description
cynse70064 document #: 38-02041 rev. ** page 13 of 124 6.0 clocks cynse70064 receives the clk2x and phs_l signals. it uses the phs_l signal to divide clk2x and generate an internal clk, as shown in figure 6-1 . the cynse70064 uses clk2x and clk for internal operations. figure 6-1. cynse70064 clocks (clk2x and phs_l) 7.0 registers all registers in the cynse70064 are 68 bits wide. the cynse70064 contains 16 pairs of comparand storage registers, eight pairs of gmrs, eight search successful index registers and one each of cmd, information, burst read, burst write, and next-free address registers. table 7-1 provides an overview of all the cynse70064 registers. the registers are ordered in ascending address order. each register group is then described in the following subsections. 7.1 comparand registers the device contains 32 68-bit comparand registers (16 pairs) dynamically selected in every search operation to store the comparand presented on the dq bus. the learn command will later use these registers when executed. the cynse70064 stores the search command ? s cycle a comparand in the even-numbered register and the cycle b comparand in the odd-numbered register, as shown in figure 7-1 . table 7-1. register overview address abbreviation type name 0 ? 31 comp0 ? 31 r sixteen pairs of comparand registers that store comparands from the dq bus for learning later. 32 ? 47 masks rw eight global mask register pairs. 48 ? 55 ssr0 ? 7 r eight search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next-free address register. 61 ? 63 ?? reserved. clk2x phs_l clk 135 0 68 68 1 0 3 2 5 4 7 6 30 31 index 0 15 1 address figure 7-1. comparand-register selection during search and learn instructions
cynse70064 document #: 38-02041 rev. ** page 14 of 124 7.2 mask registers the device contains 16 68-bit global mask registers (eight pairs) dynamically selected in every search operation to select the search subfield. the addressing of these registers is explained in figure 7-2 . the three-bit gmr index supplied on the command (cmd) bus can apply eight pairs of global masks during the search and write operations, as shown below. note . in 68-bit search and write operations, the host asic must program both the even and odd mask registers with the same values. each mask bit in the gmrs is used during search and write operations. in search operations, setting the mask bit to 1 enables compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. in write operations to the data or mask array, setting the mask bit to 1 enables writes; setting the mask bit to 0 disables writes at the correspondin g bit position. 7.3 search successful registers (ssr[0:7]) the device contains eight search successful registers (ssrs) to hold the index of the location where a successful search occurred. the format of each register is described in table 7-2 . the search command specifies which ssr stores the index of a specific search command in cycle b of the search instruction. subsequently, the host asic can use this register to access tha t data array, mask array, or external sram using the index as part of the indirect access address (see table 10-4 and table 10-7 ). the device with a valid bit set performs a read or write operation. all other devices suppress the operation. 7.4 command register table 7-3 describes the command register fields. table 7-2. search successful register description field range initial value description index [14:0] x index . this is the address of the 68-bit entry where a successful search occurs. the device updates this field only when the search is successful. if a hit occurs in a 136-bit entry-size quadrant, the lsb is 0. if a hit occurs in a 272-bit entry-size quadrant, the two lsbs are 00. this index updates if the device is either a local or global winner in a search operation. ? [30:15] 0 reserved . valid [31] 0 valid . during search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to 1. this bit updates only when the device is a global winner in a search operation. ? [67:32] 0 reserved . table 7-3. command register description field range initial value description srst [0] 0 software reset . if 1, this bit resets the device with the same effect as a hardware reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatically resets to a 0 after the reset has completed. deve [1] 0 device enable . if 0, it keeps the sram bus (sadr, we_l, ce_l, oe_l, and ale_l), ssf, and ssv signals in three-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to 0. it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. 001 123 245 367 489 51011 61213 71415 index 135 68 68 search and write command global mask selection 0 figure 7-2. addressing the global masks register array
cynse70064 document #: 38-02041 rev. ** page 15 of 124 7.5 information register table 7-4 describes the information register fields. tlsz [3:2] 01 table size . the host asic must program this field to configure the chips into a table of a certain size. this field affects the pipeline latency of the search and learn operations as well as the read and write accesses to the sram (sadr[21:0], ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. latency in number of clk cycles 00: one device 4 01: up to eight devices 5 10: up to 31 devices 6 11: reserved. hlat [6:4] 000 latency of hit signals . this field further adds latency to the ssf and ssv signals during search, and ack signal during sram read access by the following number of clk cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade . when set, this is the last device in the depth-cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0, ssv = 1. during nonsearch cycles, the device with this bit set drives the signals as follows: ssf = 0, ssv = 0. lram [8] 0 last device on the sram bus . when set, this device is the last device on the sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no cynse70064 device in a depth-cascaded table drives these signals, this devices drives the signals as follows: sadr = 22 ? h3fffff, ce_l = 1, we_l = 1, and ale_l = 1. oe_l is always driven by the device for which this bit is set. cfg [16:9] 00000000 database configuration . the device is divided internally into four partitions of 8k 68, each of which can be configured as 8k 68, 4k 136, or 2k 272, as follows. 00: 8k 68 01: 4k 136 10: 2k 272 11: reserved bits [10:9] apply to configuring the first partition in the address space. bits [12:11] apply to configuring the second partition in the address space. bits [14:13] apply to configuring the third partition in the address space. bits [16:15] apply to configuring the fourth partition in the address space. [67:17] 0 reserved . table 7-4. information register description field range initial value description revision [3:0] 000 [4] revision number . this is the current device revision number. numbers start at one and increment by one for each revision of the device. implementation [6:4] 000 or 001 this is the cynse70064 implementation number. reserved [7] 0 reserved . device id [11:8] 0001 or 0010 this is the device identification number. device id [12] 0 or 1 reserved . device id [15:13] 000 these are the three msbs of the device identification number. mfid [31:16] 1101_1100_0111_1111 manufacturer id . this field is the same as the manufacturer identification number and continuation bits in the tap controller. reserved [67:32] reserved . note: 4. this field may change in future versions. table 7-3. command register description (continued) field range initial value description
cynse70064 document #: 38-02041 rev. ** page 16 of 124 7.6 read burst address register table 7-5 shows the read burst address register (rburreg) fields which must be programmed before a burst read. 7.7 write burst address register description table 7-6 describes the write burst address register (wburreg) fields which must be programmed before a burst write. 7.8 nfa register bit [0] of each 68-bit data entry is specially designated for use in the operation of the learn command. for 68-bit-configured quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). every write and/or learn comma nd loads the address of the first 68-bit location that contains a 0 in the entry ? s bit[0]. this is stored in the nfa register (see table 7-7 ). if all the bits[0] in a device are set to 1, the cynse70064 asserts fulo[1:0] to 1. for 136-bit-configured quadrants, the lsb of the nfa register is always set to 0. the host asic must set both bit[0] and bit[68 ] in a 136-bit word to either 0 or 1 to indicate full or empty status. both bit[0] and bit[68] must be set to either 0 or 1, (tha t is, the 10 or 01 settings are invalid). table 7-5. read burst register description field range initial value description adr [14:0] 0 address . this is the starting address of the data or mask array during a burst read operation. it automatically increments by one for each successive read of the data or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:15] reserved . blen [27:19] 0 length of burst access . the device provides the capability to read from 4 ? 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved . table 7-6. write burst register description field range initial value description adr [14:0] 0 address . this is the starting address of the data or mask array during a burst write operation. it automatically increments by one for each successive write of the data or mask array. once the operation is complete, the contents of this field must be reini- tialized for the next operation. [18:15] reserved . blen [27:19] 0 length of burst access . the device provides the capability to write from 4 ? 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved . table 7-7. nfa register address 67 ? 15 14 ? 0 60 reserved index
cynse70064 document #: 38-02041 rev. ** page 17 of 124 8.0 nse architecture and operation overview the cynse70064 consists of 32k 68-bit storage cells referred to as data bits. there is a mask cell corresponding to each data cell. figure 8-1 shows the three organizations of the device based on the value of the cfg bits in the command register. during a search operation, the search data bit (s), data array bit (d), mask array bit (m) and the global mask bit (g) are used in the following manner to generate a match at that bit position (see table 8-1 ). the entry with a match on every bit position results in a successful search during a search operation. in order for a successful search within a device to make the device the local winner in the search operation, all 68-bit positi ons must generate a match for a 68-bit entry in 68-bit configured quadrants, or all 136-bit positions must generate a match for two consecutive even and odd 68-bit entries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits. an arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a search cycle. the global winning device drives the sram bus, ssv, and the ssf signals. in case of a search failure, the device(s) with the ldev and lram bits set drives the sram bus, ssf, and ssv signals. the cynse70064 device can be configured to contain tables of different widths, even within the same chip. figure 8-2 shows a sample configuration of different widths. table 8-1. bit position match gmd smatch 0xxx1 10xx1 11001 11100 11010 11111 data 16 k 136 data masks 8 k 272 cfg = 01010101 cfg = 10101010 data masks 32k 68 cfg = 00000000 masks figure 8-1. cynse70064 database width configuration
cynse70064 document #: 38-02041 rev. ** page 18 of 124 9.0 data and mask addressing figure 9-1 shows cynse70064 data and mask array addressing. 10.0 commands a master device such as an asic controller issues commands to the cynse70064 device using the command valid (cmdv) signal and the cmd bus. the following subsections describe the operation of the commands. 10.1 command codes the cynse70064 implements four basic commands, shown in table 10-1 . the command code must be presented to cmd[1:0] while keeping the cmdv signal high for two clk2x cycles (designated as cycles a and b). the controller asic must align the instructions using the phs_l signal. the cmd[8:2] field passes the parameters of the command in cycles a and b. table 10-1. command codes command code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, mask array, device registers, or external sram. 10 search searches the data array for a desired pattern using the specified register from the gmr array and local mask associated with each data cell. 11 learn the device has internal storage for up to 16 comparands that it can learn. the device controller can insert these entries at the next-free address (as specified by the nfa register) using the learn instruction. 4 k 136 8 k 68 8 k 68 2 k 272 cfg = 10010000 figure 8-2. multiwidth database configurations example cfg = 00000000 cfg = 10101010 67 0 68 0 1 2 3 32767 283 0 68 68 3 2 1 0 7 6 5 4 32764 32765 32766 32767 68 68 cfg = 01010101 135 0 68 68 1 0 3 2 5 4 7 6 32766 32767 (68-bit configuration) (272-bit configuration) (136-bit configuration) 32k 8k 64k figure 9-1. addressing of the cynse70064 data and mask arrays
cynse70064 document #: 38-02041 rev. ** page 19 of 124 10.2 commands and command parameters table 10-2 lists the cmd bus fields that contain the cynse70064 command parameters and their respective cycles. each command is described separately in the subsections that follow. 10.3 read command the read can be a single read of a data array, a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read of the data (cmd[2] = 1) or mask array locations using an internal auto-incrementing address register (rburadr). a description of each type is provided in table 10-3 . a single-location read operation lasts six cycles, as shown in figure 10-1 . the burst read adds two cycles for each successive read. the sadr[21:20] bits supplied in the read instruction cycle a drives sadr[21:20] signals during the read of an sram location. table 10-2. command parameters cmdcyc876543210 read a sadr[21] sadr[20] x 0 0 0 0 = single 1 = burst 00 b 0 0 0 0 0 0 0 = single 1 = burst 00 write a sadr[21] sadr[20] x gmr index [2:0] 0 = single 1 = burst 01 b 0 0 0 gmr index [2:0] 0 = single 1 = burst 01 search a sadr[21] sadr[20] x gmr index 2:0] 68-bit or 136-bit: 0 272-bit: 1 in first cycle 0 in second cycle 10 b ssri[2:0] comparand register index 1 0 learn [5] a sadr[21] sadr[20] x comparand register index 1 1 b0 0 mode 0: 68-bit 1: 136-bit comparand register index 1 1 table 10-3. read command parameters cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data array, or mask array as a burst. the internal register (rburadr) specifies the starting address and the length of the data transfer from the data or mask array, and it auto-incre- ments the address for each access. all other access information is applied on the dq bus. note . the device registers and external sram can only be read in single-read mode. note: 5. the 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the learn instruction.
cynse70064 document #: 38-02041 rev. ** page 20 of 124 the single read operation takes six clock cycles, in the following sequence. cycle 1 : the host asic applies the read instruction on the cmd[1:0] (cmd[2] = 0) using cmdv = 1 and the dq bus supplies the address, as shown in table 10-4 and table 10-5 . the host asic selects the cynse70064 for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the cynse70064 with the ldev bit set. the host asic also supplies sadr[21:20] on cmd[8:7] in cycle a of the read instruction if the read is directed to the external sram. cycle 2 : the host asic floats dq[67:0] to three-state condition. cycle 3 : the host asic keeps dq[67:0] in three-state condition. cycle 4 : the selected device starts to drive the dq[67:0] bus, and drives the ack signal from z to low. cycle 5 : the selected device drives the read data from the addressed location on the dq[67:0] bus, and drives the ack signal high. cycle 6 : the selected device floats the dq[67:0] to three-state condition and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to three-state condition. the read instruction is comp lete, and a new operation can begin. note that the latency of the sram read will be different than the one described above (see subsection 12.2, ? sram pio access ? on page 102). table 10-4 lists and describes the format of the read address for a data array, mask array, or sram. table 10-4. read address format for data array, mask array, or sram dq[67:30] dq[29] dq[28:26] dq[25:21] dq[20:19] dq[18:15] dq[14:0] reserved 0: direct 1: indirect ssri (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the data array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [6] reserved 0: direct 1: indirect ssri (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the mask array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [6] reserved 0: direct 1: indirect ssri (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the sram location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} [6] note: 6. ? | ? stands for logical or operation. ? {} ? stands for concatenation operator. cycle cycle cycle cycle cycle cycle read address ff data 1 2 345 6 clk2x cmdv cmd[1:0] ack dq cmd[8:2] a b phs_l figure 10-1. single-location read cycle timing
cynse70064 document #: 38-02041 rev. ** page 21 of 124 table 10-5 describes the read address format for the internal registers. figure 10-2 illustrates the timing diagram for the burst read of the data or mask array. the read operation lasts 4 + 2n clk cycles (where n is the number of accesses in the burst specified by the blen field of the rburreg) in the sequence shown below. this operation assumes that the host asic has programmed the rburreg with the starting address (adr) and the length of the transfer (blen) before initiating the burst read command. cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1 and the address supplied on the dq bus, as shown in table 10-6 . the host asic selects the cynse70064 where id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the cynse70064 with the ldev bit set. cycle 2 : the host asic floats dq[67:0] to the three-state condition. cycle 3 : the host asic keeps dq[67:0] in the three-state condition. cycle 4 : the selected device starts to drive the dq[67:0] bus and drives ack and eot from z to low. cycle 5: the selected device drives the read data from the addressed location on the dq[67:0] bus, and drives the ack signal high. cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (blen) field of rburreg are complete. on the last transfer, the cynse70064 drives the eot signal high. cycle (4 + 2n): the selected device drives the dq[67:0] to the three-state condition, and drives the ack and eot signals low. at the termination of cycle (4 + 2n), the selected device floats the ack line to the three-state condition. the burst read inst ruction is complete, and a new operation can begin. table 10-6 describes the read address format for data and mask arrays for burst read operations. table 10-5. read address format for internal registers dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address table 10-6. read address format for data and mask arrays dq[67:26] dq[25:21] dq[20:19] dq[18:15] dq[14:0] reserved id 00: data array reserved do not care . these 15 bits come from the internal register (rburadr) which increments for each access. reserved id 01: mask array reserved do not care . these 15 bits come from the internal register (rburadr) which increments for each access. cmdv cmd[1:0] ack eot dq ff ff data1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 data0 data2 ff data3 ff phs_l cmd[8:2] address a b read clk2x figure 10-2. burst read of the data and mask arrays (blen = 4)
cynse70064 document #: 38-02041 rev. ** page 22 of 124 10.4 write command the write can be a single write of a data array, mask array, register, or external sram location (cmd[2] = 0). it can be a burs t write (cmd[2] = 1) using an internal auto-incrementing address register (wburadr) of the data or mask array locations. a single-location write is a 3-cycle operation, as shown in figure 10-3 . the burst write adds one extra cycle for each successive location write. the following is the write operation sequence, and table 10-7 shows the write address format for the data array, the mask array, or single-write sram. table 10-8 shows the write address format for the internal registers. cycle 1a: the host asic applies the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic also supplies the gmr index to mask the write to the data or mask array location on cmd[5:3]. for sram writes, the host asic must supply the sadr[21:20] on cmd[8:7]. cycle 1b: the host asic continues to apply the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in cmd[5:3].the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. cycle 2: the host asic drives the dq[67:0] with the data to be written to the data array, mask array, or register location of the selected device. cycle 3: idle cycle. at the termination of cycle 3, another operation can begin. note . the latency of the sram write will be different than the one described above (see subsection 12.2, ? sram pio access ? on page 102). table 10-7. write address format for data array, mask array, or sram (single write) dq [67:30] dq[29] dq[28:26] dq [25:21] dq[20:19] dq [18:15] dq[14:0] reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of data array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [7] reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of the mask array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [7] reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of sram location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [7] note: 7. ? | ? stands for logical or operation. ? {} ? stands for concatenation operator. cycle 2 cycle 3 write address data cmdv cmd[1:0] dq x cycle 1 cycle 0 cycle 4 cmd[8:2] b phs_l a clk2x figure 10-3. single write cycle timing
cynse70064 document #: 38-02041 rev. ** page 23 of 124 figure 10-4 shows the timing diagram of a burst write operation of the data or mask array. the burst write operation lasts for (n + 2) clk cycles. n signifies the number of accesses in the burst as specified in the ble n field of the wburreg register. the following is the block write operation sequence. this operation assumes that the host asic has programmed the wburreg with the starting address (adr) and the length of transfer (blen) before initiating a burst write command. cycle 1a : the host asic applies the write instruction to the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus, as shown in table 10-9 . the host asic also supplies the gmr index to mask the write to the data or mask array locations in cmd[5:3]. cycle 1b : the host asic continues to apply the write instruction on the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in cmd[5:3]. the host asic selects the device for which id[4:0] matches the dq[25:21] lines. it selects all the devices when dq[25:21] = 11111. cycle 2 : the host asic drives the dq[67:0] with the data to be written to the data or mask array location of the selected device. the cynse70064 writes the data from the dq[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in the gmr specified by the index cmd[5:3] supplied in cycle 1. cycles 3 to n + 1 : the host asic drives the dq[67:0] with the data to be written to the next data or mask array location (addressed by the auto-increment adr field of the wburreg register) of the selected device. the cynse70064 writes the data on the dq[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in the gmr specified by the index cmd[5:3] supplied in cycle 1. the cynse70064 drives the eot signal low from cycle 3 to cycle n; the cynse70064 drives the eot signal high in cycle n + 1 (n is specified in the blen field of the wburreg). cycle n + 2: thecynse70064 drives the eot signal low. at the termination of cycle n + 2, the cynse70064 floats the eot signal to a three-state operation, and a new instruction can begin. table 10-8. write address format for internal registers dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address 1 data0 data1 data2 x data3 write address cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle cmd[1:0] dq clk2x eot cmd[8:2] a b phs_l cmdv figure 10-4. burst write of the data and mask arrays (blen = 4)
cynse70064 document #: 38-02041 rev. ** page 24 of 124 10.5 search command this subsection describes the following: 68-bit search on tables configured as 68 using one device 68-bit search on tables configured as 68 using up to eight devices 68-bit search on tables configured as 68 using up to 31 devices 136-bit search on tables configured as 136 using one device 136-bit search on tables configured as 136 using up to eight devices 136-bit search on tables configured as 136 using up to 31 devices 272-bit search on tables configured as 272 using one device 272-bit search on tables configured as 272 using up to eight devices 272-bit search on tables configured as 272 using up to 31 devices mixed-size searches on tables configured with different widths using an cynse70064. 10.6 68-bit search on tables configured as 68 using a single cynse70064 device figure 10-5 shows the timing diagram for a search command in the 68-bit-configured table (cfg = 00000000) consisting of a single device for one set of parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-6 . table 10-9. write address format for data and mask array (burst write) dq[67:26] dq[25:21] dq[20:19] dq[18:15] dq[14:0] reserved id 00: data array reserved do not care . these 15 bits come from the internal register (wburadr), which increments with each access. reserved id 01: mask array reserved do not care . these 15 bits come from the internal register (wburadr), which increments with each access.
cynse70064 document #: 38-02041 rev. ** page 25 of 124 the following is the sequence of operation for a single 68-bit search command (also refer to command and command param- eters, subsection 10.2 on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data to be compared. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and to apply search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for information on ssr[0:7]). the dq[67:0] continues to carry the 68-bit data to be compare d. note . for 68-bit searches, the host asic must supply the same 68-bit data on dq[67:0] during both cycles a and b. the even and odd pair of gmrs selected for the compare must be programmed with the same value. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l hit hit miss miss cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 000, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search3 search4 d1 d2 d3 d4 a1 a3 01 01 01 01 search1 search3 a b a b a b a b 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 figure 10-5. timing diagram for 68-bit search in x 68 table (one device) lho[0] 6543210 lhi lho[1] bhi[2:0] dq[67:0] sram cynse70064 cmdv, cmd8:0] bhi[2:0] ssf, ssv figure 10-6. timing diagram for 68-bit search in x 68 table (one device)
cynse70064 document #: 38-02041 rev. ** page 26 of 124 the logical 68-bit search operation is shown in figure 10-7 . the entire table consisting of 68-bit entries is compared to a 68-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word specified by the identical value in both even and odd gmr pairs selected by the gmr index in the command ? s cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand register index in the command ? s cycle b. in a 68 configu- ration, only the even comparand register can be subsequently used by the learn command. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 68-bit searches in 68-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 10-10 . the latency of a search from command to sram access cycle is 4 for a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-11 . 10.7 68-bit search on tables configured as 68 using up to eight cynse70064 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-8 . the following are the parameters programmed into the eight devices. first seven devices (devices 0 ? 6): cfg = 00000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. eighth device (device 7): cfg = 00000000, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. table 10-10. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 68 bits 4 1 ? 8 (tlsz = 01) 256k 68 bits 5 1 ? 31 (tlsz = 10) 992k 68 bits 6 table 10-11. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 00000000 67 0 location 0 1 2 3 32767 (68-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 67 0 67 0 (first matching entry) l figure 10-7. 68 table with one device
cynse70064 document #: 38-02041 rev. ** page 27 of 124 note . all eight devices must be programmed with the same values for tlsz and hlat. only the last device in the table (device number 7 in this case) must be programmed with lram = 1 and ldev = 1. all other upstream devices (devices 0 through 6 in this case) must be programmed with lram = 0 and ldev = 0. figure 10-9 shows the timing diagram for a search command in the 68-bit-configured table of eight devices for device number 0. figure 10-10 shows the timing diagram for a search command in the 68-bit-configured table of eight devices for device number 1. figure 10-11 shows the timing diagram for a search command in the 68-bit-configured table of eight devices for device number 7 (the last device in this specific table). for these timing diagrams four 68-bit searches are performed sequentially. hit/miss a ssump- tions were made as shown below in table 10-12 . table 10-12. hit/miss assumption search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss devices 2 ? 6missmissmissmiss device 7 miss miss hit hit
cynse70064 document #: 38-02041 rev. ** page 28 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 10-8. hardware diagram for a table with eight devices
cynse70064 document #: 38-02041 rev. ** page 29 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (this cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search3 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z device is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 on this (miss on this device.) lho[1:0] search2 (miss device.) figure 10-9. timing diagram for 68-bit search device number 0
cynse70064 document #: 38-02041 rev. ** page 30 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search3 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local winner but not global winner.) (miss on this device.) |(lhi[6:0]) lho[1:0] z 0 z z 0 z z 1 z on this device. ) (this device is global winner.) figure 10-10. timing diagram for 68-bit search device number 1
cynse70064 document #: 38-02041 rev. ** page 31 of 124 the following is the sequence of operation for a single 68-bit search command (also refer to ? command and command param- eters, ? subsection 10.2 on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data t o be compared. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and to apply search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 14 for a description of ssr[0:7]). the dq[67:0] continues to carry the 68-bit data to be compared. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[8:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 010, tlsz = 01, lram = 1, ldev = 1. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv search1 search2 search3 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local winner but not global winner.) |(lhi[6:0]) lho[1:0] on this device .) (miss on this ) device. 0 z 0 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 search4 (global winner.) z figure 10-11. timing diagram for 68-bit search device number 7 (last device)
cynse70064 document #: 38-02041 rev. ** page 32 of 124 note . for 68-bit searches, the host asic must supply the same 68-bit data on dq[67:0] during both cycles a and b, and the even and odd pairs of gmrs selected for the comparison must be programmed with the same value. the logical 68-bit search operation is shown in figure 10-12 . the entire table with eight devices of 68-bit entries is compared to a 68-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices and selected by the gmr index in the command ? s cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. in the 68 configuration, only the even comparand register can subsequently be used by the learn command in one of the devices (only the first non-full device). the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). the global winning device will drive the bus in a specific cycle. on a global miss cycle the device with lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving device for ssf and ssv signals) will be the default drive r for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 68-bit searches in 68-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 10-13 . the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01). ssv and ssf also shift further to the right for different values of hlat, as specified in table 10-14 . table 10-13. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 68 bits 4 1 ? 8 (tlsz = 01) 256k 68 bits 5 1 ? 31 (tlsz = 10) 992k 68 bits 6 table 10-14. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 00000000 67 0 location 0 1 2 3 262143 (68-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 67 0 67 0 (first matching entry) l must be same in each of the eight devices will be same in each of the eight devices figure 10-12. x68 table with eight devices
cynse70064 document #: 38-02041 rev. ** page 33 of 124 10.8 68-bit search on tables configured as 68 using up to 31 cynse70064 devices the hardware diagram of the search subsystem of 31 devices is shown in figure 10-13 . each of the four blocks in the diagram represents eight cynse70064 devices (except the last, which has seven devices). the diagram for a block of eight devices is shown in figure 10-14 . the following are the parameters programmed into the 31 devices. first thirty devices (devices 0 ? 29): cfg = 00000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 00000000, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same values for tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-15 . for the purpose of illustrating the timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 10-15 shows the timing diagram for a search command in the 68-bit-configured table of 31 devices for each of the eight devices in block 0. figure 10-16 shows a timing diagram for a search command in the 68-bit-configured table of 31 devices for the all the devices in block number 1 (above the winning device in that block). figure 10-17 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. figure 10-18 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-19 , figure 10-20 , and figure 10-21 show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winn ing device, respectively, for block number 2. figure 10-22 , figure 10-23 , figure 10-24 , and figure 10-25 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device except the last device (device 30), respectively, for block number 3. the 68-bit search operation is pipelined and executes as follows. four cycles from the search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycle after the search command, the devices in a block arbitr ate for a winner amongst them (a ? block ? being defined as less than or equal to eight devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism). in the sixth cycle after the search command, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the winning block is the global winning device for a search operation. table 10-15. hit/miss assumptions search number 1 2 3 4 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
cynse70064 document #: 38-02041 rev. ** page 34 of 124 bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24 ? 30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 10-13. hardware diagram for a table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 35 of 124 figure 10-14. hardware diagram for a block of up to eight devices lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] bhi[2:0] ssv, ssf cynse70064 #6
cynse70064 document #: 38-02041 rev. ** page 36 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-15. timing diagram for each device in block number 0 (miss on each device)
cynse70064 document #: 38-02041 rev. ** page 37 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. ote: |(bhi[2:0)] stands for the boolean ? or ? of the entire bus bhi[2:0]. ote: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. ote: each bit in bho[2:0] is the same logical signal. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-16. timing diagram for each device above the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 38 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (this device global winner) |(lhi[6:0]) 0 bho[2:0] 0 a3 z z z z z z figure 10-17. timing diagram for globally winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 39 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-18. timing diagram for devices below the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 40 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-19. timing diagram for devices above the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 41 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (global winner.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z figure 10-20. timing diagram for globally winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 42 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z (miss on this device.) figure 10-21. timing diagram for devices below the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 43 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) figure 10-22. timing diagram for devices above the winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 44 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (hit but not global i(bhi[2:0]) 0 (global winner .) search3 |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z winner.) (miss on this device.) (miss on this device.) figure 10-23. timing diagram for globally winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 45 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) figure 10-24. timing diagram for devices below the winning device in block number 3 (except the last device [device 30])
cynse70064 document #: 38-02041 rev. ** page 46 of 124 the following is the sequence of operation for a single 68-bit search command (also refer to the ? command and command parameters, ? subsection 10.2 on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data t o be compared. the cmd[2] signal must be driven to a logic 0. cycle b : the host asic continues to drive the cmdv high and applies search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for the description of ssr[0:7]). the dq[67:0] continues to carry the 68-bit data to be compared. note . for 68-bit searches, the host asic must supply the same 68-bit data on dq[67:0] during both cycles a and b and the even and odd pair of global mask registers selected for the compare must be programmed with the same value. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 00000000, hlat = 001, tlsz = 10, lram = 1, ldev = 1. note: |(bhi[2:0)] stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 lho[1:0] 0 (hit on some device (global miss; this device default driver.) i(bhi[2:0]) 0 (hit on some device above.) search3 |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 above.) 0 0 z z 0 1 figure 10-25. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table) (hit on some device above.)
cynse70064 document #: 38-02041 rev. ** page 47 of 124 the logical 68-bit search operation is shown in figure 10-26 . the entire table (31 devices of 68-bit entries) is compared to a 68-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices and selected by the gmr index in the command ? s cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the comparand register index in command ? s cycle b. in the 68 configuration, the even comparand register can be subsequently used by the learn command only in the first non-full device. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 and ldev = 1 will b e the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 68-bit searches in 68-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 10-16 . for up to 31 devices in the table (tlsz = 10), search latency from command to sram access cycle is 6. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-17 . table 10-16. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 68 bits 4 1 ? 8 (tlsz = 01) 256k 68 bits 5 1 ? 31 (tlsz = 10) 996k 68 bits 6 table 10-17. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 00000000 67 0 location 0 1 2 3 1015807 (68-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 67 0 67 0 (first matching entry) l must be same in each of the 31 devices will be same in each of the 31 devices figure 10-26. 68 table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 48 of 124 10.9 136-bit search on tables configured as 136 using a single cynse70064 device figure 10-27 shows the timing diagram for a search command in the 136-bit-configured table (cfg = 01010101) consisting of a single device for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-28 . the following is the operation sequence for a single 136-bit search command (also refer to ? command and command param- eters, ? subsection 10.2 on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared against all even locations. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and applies the command code of search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 14 for the description of ssr[0:7]). the dq[67:0] is driven with 68-bit data ([67:0]), compared to all odd locations. cycle clk2x cmdv cmd[1:0] ce_l oe_l hit hit miss miss cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search3 search4 a1 a3 01 01 01 01 search1 search3 a b a b a b a b 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 a b a b a b a b dq d1 d2 d3 d4 figure 10-27. timing diagram for 136-bit search (one device) lho[0] 6543210 lhi lho[1] bhi[2:0] dq[67:0] sram cynse70064 cmdv, cmd[8:0] bho[2:0] ssf, ssv figure 10-28. hardware diagram for a table with one device
cynse70064 document #: 38-02041 rev. ** page 49 of 124 note . for 136-bit searches, the host asic must supply two distinct 68-bit data words on dq[67:0] during cycles a and b. the even-numbered gmr of the pair specified by the gmr index is used for masking the word in cycle a. the odd-numbered gmr of the pair specified by the gmr index is used for masking the word in cycle b. the logical 136-bit search operation is shown in figure 10-29 . the entire table of 136-bit entries is compared to a 136-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and the local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by the gmr index in the command ? s cycle a. the 136-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand register index in the command ? s cycle b. the two comparand registers can subsequently be used by the learn command with the even comparand register stored in an even location, and the odd comparand register stored in an adjacent odd location. the word k (presented on the dq bus in cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). note . the matching address is always going to an even address for a 136-bit search. the search command is a pipelined operation that executes searches at half the rate of the frequency of clk2x for 136-bit searches in 136-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 10-18 . for a single device in the table with tlsz = 00, the latency of the search from command to sram access cycle is 4. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-19 . table 10-18. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 136 bits 4 1 ? 8 (tlsz = 01) 128k 136 bits 5 1 ? 31 (tlsz = 10) 496k 136 bits 6 table 10-19. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 01010101 135 0 location 0 2 4 6 32766 (136-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 135 0 67 0 (first matching entry) l a b even odd figure 10-29. 136 table with one device
cynse70064 document #: 38-02041 rev. ** page 50 of 124 10.10 136-bit search on tables configured as 136 using up to eight cynse70064 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-30 . the following are parameters programmed into the eight devices. first seven devices (devices 0 ? 6): cfg = 01010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. eighth device (device 7): cfg = 01010101, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note . all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 10-31 shows the timing diagram for a search command in the 136-bit-configured table of eight devices for device 0. figure 10-32 shows the timing diagram for a search command in the 136-bit-configured table consisting of eight devices for device number 1. figure 10-33 shows the timing diagram for a search command in the 136-bit configured table consisting of eight devices for device number 7 (the last device in this specific table). for these timing diagrams, four 136-bit searches are perf ormed sequentially, and the following hit/miss assumptions were made (see table 10-20 ). table 10-20. hit/miss assumption search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss devices 2 ? 6 miss miss miss miss device 7 miss miss hit hit
cynse70064 document #: 38-02041 rev. ** page 51 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 10-30. hardware diagram for a table with eight devices
cynse70064 document #: 38-02041 rev. ** page 52 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l (this cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 01010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. ote: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z device is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 (miss on this device.) (miss on this device.) lho[1:0] a b a b a b a b dq d1 d2 d3 d4 figure 10-31. timing diagram for 136-bit search device number 0
cynse70064 document #: 38-02041 rev. ** page 53 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local but not global winner.) (miss on this device.) lhi[6:0] lho[1:0] z 0 z z 0 z z 1 z on this device.) (this device global winner.) a b a b a b a b dq d1 d2 d3 d4 figure 10-32. timing diagram for 136-bit search device number 1
cynse70064 document #: 38-02041 rev. ** page 54 of 124 the following is the sequence of operation for a single 136-bit search command (also see subsection 10.2, ? commands and command parameters ? on page 19). cycle a : the host asic drives cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven by this device on sadr[21:20] if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) in order to be compared against all even locations. the cmd[2] signal must be driven to a logic 0. cycle b : the host asic continues to drive cmdv high and to apply the command code for search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the ssr index that will be used for storing the address of the matching entry and the hit flag (see page 14 for the description of ssr[0:7]). the dq[67:0] is driven with 68-bit data ([67:0]) compared against all odd locations. cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss cmd[8:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 010, tlsz = 01, lram = 1, ldev = 1. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local but not global winner.) (global winner.) |(lhi[6:0]) lho[1:0] on this device.) (miss on this device.) 0 z 0 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-33. timing diagram for 136-bit search device number 7 (last device)
cynse70064 document #: 38-02041 rev. ** page 55 of 124 the logical 136-bit search operation is shown in figure 10-34 . the entire table (eight devices of 136-bit entries) is compared to a 136-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by the gmr index in the command ? s cycle a. the 136-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in the even and odd comparand registers specified by the comparand register index in the command ? s cycle b. in 136 configurations, the even and odd comparand registers can subsequently be used by the learn command in only one of the devices (the first non-full device). the word k (presented on the dq bus in cycles a and b of the command) is compared to each entry in the table starting at location 0. the first matching entry ? s location, address l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note . during 136-bit searches of 136-bit-configured tables, the search hit will always be at an even address. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 136-bit searches in 136-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 10-21 . for one to eight devices in the table and tlsz = 01, the latency of a search from command to sram access cycle is 5. in addition , ssv and ssf shift further to the right for different values of hlat as specified in table 10-22 . table 10-21. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 136 bits 4 1 ? 8 (tlsz = 01) 128k 136 bits 5 1 ? 31 (tlsz = 10) 496k 136 bits 6 table 10-22. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 01010101 135 0 location 0 2 4 6 262142 (136-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 135 0 67 0 (first matching entry) l a b even odd will be same in each of the eight devices must be same in each of the eight devices figure 10-34. 136 table with eight devices
cynse70064 document #: 38-02041 rev. ** page 56 of 124 10.11 136-bit search on tables configured as 136 using up to 31 cynse70064 devices the hardware diagram of the search subsystem of 31 devices is shown in figure 10-35 . each of the four blocks in the diagram represents a block of eight cynse70064 devices (except the last, which has seven devices).the diagram for a block of eight devices is shown in figure 10-36 . following are the parameters programmed into the 31 devices. first thirty devices (devices 0 ? 29): cfg = 01010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 01010101, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-23 . for the purpose of illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 10-37 shows the timing diagram for a search command in the 136-bit-configured table (31 devices) for each of the eight devices in block number 0. figure 10-38 shows the timing diagram for search command in the 68-bit-configured table (31 devices) for all the devices in block number 1 above the winning device in that block. figure 10-39 shows the timing diagram for the globally winning device (the final winner within its own block and all blocks) in block number 1. figure 10-40 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-41 , figure 10-42 , and figure 10-43 respectively show the timing diagrams of the devices above globally winning device, the globally winning device and devices below the global ly winning device for block number 2. figure 10-44 , figure 10-45 , figure 10-46 , and figure 10-47 respectively show the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 30), and the last device (device 30) for block number 3. the 136-bit search operation is pipelined and executes as follows. four cycles from the search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycle after the search command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner amongst them. in the sixth cycle after the search command, the blocks (of devices) resolve the winning block throu gh the bhi[2:0] and bho[2:0] signalling mechanism. the winning device in the winning block is the global winning device for a sear ch operation. table 10-23. hit/miss assumption search number 1 2 3 4 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
cynse70064 document #: 38-02041 rev. ** page 57 of 124 bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24 ? 30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 10-35. hardware diagram for a table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 58 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] bhi[2:0] ssv, ssf figure 10-36. hardware diagram for a block of up to eight devices
cynse70064 document #: 38-02041 rev. ** page 59 of 124 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. ote: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. ote: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. ote: each bit in bho[2:0] is the same logical signal. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b d1 d2 d3 d4 figure 10-37. timing diagram for each device in block number 0 (miss on each device)
cynse70064 document #: 38-02041 rev. ** page 60 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-38. timing diagram for each device above the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 61 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 a b a b a b a b dq d1 d2 d3 d4 1zz 1z 1z 0 z 0 z z figure 10-39. timing diagram for globally winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 62 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0] stands for the boolean ? or ? of the entire4 bus bhi[2:0]. note: |(lhi(6:0) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-40. timing diagram for devices below the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 63 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-41. timing diagram for devices above the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 64 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (global winner.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z a b a b a b a b dq d1 d2 d3 d4 figure 10-42. timing diagram for globally winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 65 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. ote: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. ote: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. ote: each bit in bho[2:0] is the same logical signal. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (miss on this device) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) figure 10-43. timing diagram for devices below the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 66 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 figure 10-44. timing diagram for devices above the winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 67 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. ote: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. ote: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. ote: each bit in bho[2:0] is the same logical signal. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (hit but not global (miss on this device.) i(bhi[2:0]) 0 (global winner.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z winner.) a b a b a b a b dq d1 d2 d3 d4 figure 10-45. timing diagram for globally winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 68 of 124 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 figure 10-46. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)
cynse70064 document #: 38-02041 rev. ** page 69 of 124 the following is the sequence of operation for a single 136-bit search command (also refer to ? command and command parameters, ? subsection 10.2 on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:6 8]) in order to be compared against all even locations. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and to apply search command code (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for the description of ssr[0:7]). the dq[67:0] is driven with 68-bit data ([67:0])to be compared against all odd locations. the logical 136-bit search operation is as shown in the following figure 10-48 . the entire table of 31 devices (consisting of 136-bit entries) is compared against a 136-bit word k that is presented on the dq bus in cycles a and b of the command using the gmr and local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by the gmr index in the command ? s cycle a. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[8:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 01010101, hlat = 001, tlsz = 10, lram = 1, ldev = 1. ote: |(bhi[2:0)] stands for the boolean ? or ? of the entire bus bhi[2:0]. ote: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. ote: each bit in bho[2:0] is the same logical signal. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 lho[1:0] 0 (hit on some device (global miss; this device default driver.) i(bhi[2:0]) 0 (hit on some device search3 |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 above.) above.) 0 0 z z 0 1 a b a b a b a b dq d1 d2 d3 d4 (hit on some device above.) figure 10-47. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table)
cynse70064 document #: 38-02041 rev. ** page 70 of 124 the 136-bit word k that is presented on the dq bus in cycles a and b of the command is also stored in the even and odd comparand registers specified by the comparand register index in the command ? s cycle b. in 136 configurations, the even and odd comparand registers can subsequently be used by the learn command in only the first non-full device. note . the learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. the word k that is presented on the dq bus in cycles a and b of the command is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see section 12.0, ? sram addressing ? on page 101). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note . during 136-bit searches of 136-bit-configured tables, the search hit will always be at an even address. the search command is a pipelined operation. it executes a search at half the rate of the frequency of clk2x for 136-bit search es in 136-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 10-24 . the latency of a search from command to the sram access cycle is 6 for 1 ? 31 devices in the table and where tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-25 . table 10-24. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 136 bits 4 1 ? 8 (tlsz = 01) 128k 136 bits 5 1 ? 31 (tlsz = 10) 496k 136 bits 6 table 10-25. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 01010101 135 0 location 0 2 4 6 1015806 (136-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 135 0 67 0 (first matching entry) l a b even odd will be same in each of the 31 devices must be same in each of the 31 devices figure 10-48. 136 table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 71 of 124 10.12 272-bit search on tables configured as ? 272 using a single cynse70064 device figure 10-49 shows the timing diagram for a search command in the 272-bit-configured table (cfg = 10101010) consisting of a single device for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-50 . the following is the sequence of operation for a single 136-bit search command (also refer to subsection 10.2, ? commands and command parameters ? on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched. dq[67:0] must be driven with the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68-bits-word page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a 272-bit search. cmd[8:3] in this cycle is ignored. cycle clk2x cmdv cmd[1:0] ce_l oe_l hit miss cmd[8:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 10101010, hlat = 001, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[21:0] ssf ssv ale_l search1 search2 a1 01 01 search1 search2 a b a b a b a b 0 1 0 0 1 1 0 0 1 1 0 1 0 0 a b c d a b c d dq d1 d2 cmd[2] 1 0 1 10 1 figure 10-49. timing diagram for 272-bit search (one device) lho[0] 6543210 lhi lho[1] bhi[2:0] dq[67:0] sram cynse70064 cmdv, cmd[8:0] bho[2:0] ssf, ssv figure 10-50. hardware diagram for a table with one device
cynse70064 document #: 38-02041 rev. ** page 72 of 124 cycle b : the host asic continues to drive the cmdv high and continues to apply the command code of search command (10) on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([204:136]) to be compared to all locations 1 in the four 68-bits- word page. cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-b it data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logic 0. cycle d : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit fl ag (see page 14 for the description of ssr[0:7]). the dq[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locat ions 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 tables. note . for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs that apply to dq data in cycles c and d. the logical 272-bit search operation is shown in figure 10-51 . the entire table of 272-bit entries is compared to a 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command ? s cycles a and c. the 272-bit word k that is presented on the dq bus in cycles a, b, c and d of the command is compared with each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on sadr[21:0] lines (see ? sram addressing ? on page 101). note . the matching address is always going to be location 0 in a four-entry page for a 272-bit search (two lsbs of the matching index will be 00). figure 10-51. 272 table with one device the search command is a pipelined operation and executes at one-fourth the rate of the frequency of clk2x for 272-bit searches in 272-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-26 . the latency of a search from command to sram access cycle is 4 for only a single device in the table and tlsz = 00. in addition , ssv and ssf shift further to the right for different values of hlat, as specified in table 10-27 . table 10-26. the latency of search from c and d cycles to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 8k 272 bits 4 1 ? 8 (tlsz = 01) 64k 272 bits 5 1 ? 31 (tlsz = 10) 248k 272 bits 6 table 10-27. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 cfg = 10101010 271 0 location 0 4 8 12 32764 (272-bit configuration) address k gmr 271 0 (first matching entry) l a b 01 c d 23
cynse70064 document #: 38-02041 rev. ** page 73 of 124 10.13 272-bit search on tables x272-configured using up to eight cynse70064 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-52 . the following are the parameters programmed in the eight devices. first seven devices (devices 0 ? 6): cfg = 10101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0. eighth device (device 7): cfg = 10101010, tlsz = 01, hlat = 000, lram = 1, and ldev = 1. note . all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 10-53 shows the timing diagram for a search command in the 272-bit-configured table of eight devices for device number 0. figure 10-54 shows the timing diagram for a search command in the 272-bit-configured table of eight devices for device number 1. figure 10-55 shows the timing diagram for a search command in the 272-bit-configured table of eight devices for device number 7 (the last device in this specific table). for these timing diagrams three 272-bit searches are performed sequentially. the following hit/miss assumptions were made as shown in table 10-28 . 100 4 101 5 110 6 111 7 table 10-28. hit/miss assumption search number 1 2 3 device 0 hit miss miss device 1 miss hit miss devices 2 ? 6 miss miss miss device 7 miss miss miss table 10-27. shift of ssf and ssv from sadr (continued) hlat number of clk cycles
cynse70064 document #: 38-02041 rev. ** page 74 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 10-52. hardware diagram for a table with eight devices
cynse70064 document #: 38-02041 rev. ** page 75 of 124 cycle clk2x cmdv ce_l oe_l (this we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ale_l search1 search2 search3 a1 z z z z z z z 0 device is the global winner.) |(lhi[6:0]) 0 (miss on this device.) (miss on this device.) lho[1:0] cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z z 0 1 ssv z z 1 ssf z 1 z figure 10-53. timing diagram for 272-bit search device number 0
cynse70064 document #: 38-02041 rev. ** page 76 of 124 cycle clk2x ce_l oe_l (miss we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 fg = 10101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0. ote: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 a2 z z z z 1 1 z z |(lhi[6:0]) lho[1:0] z 0 z 1 z on this device.) (this device is global winner.) z z 0 (miss search3 on this device.) cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 figure 10-54. timing diagram for 272-bit search device number 1
cynse70064 document #: 38-02041 rev. ** page 77 of 124 the following is the sequence of operation for a single 272-bit search command (also see ? commands and command param- eters ? on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched in this operation. dq[67:0] must be driven with the 68-bit data ([271:204]) to be compared against all locations 0 in the four-word 68-bit page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a 272 bit search. cmd[8:3] in this cycle is ignored. cycle b : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([203:136]) to be compared against all locations 1 in the four 68-bits-word page. cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-b it data ([135:68]) to be compared against all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logic 0. cycle d : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit fl ag (see page 14 for the description of ssr[0:7]). the dq[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locat ions 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 tables. note . for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the eight devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the eight devices that apply to dq data in cycles c and d. cycle clk2x cmdv ce_l oe_l (miss 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 01, lram = 1, ldev = 1. note: |(lhi[6:0]) stands for the boolean ? or ? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv search1 search2 search3 0 (global miss.) |(lhi[6:0]) lho[1:0] on this device.) (miss on this device.) 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 0 cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 0 z z 1 z z 0 0 z 0 figure 10-55. timing diagram for 272-bit search device number 7 (last device)
cynse70064 document #: 38-02041 rev. ** page 78 of 124 the logical 272-bit search operation is shown in figure 10-56 . the entire table of 272-bit entries is compared to a 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and the local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command ? s cycles a and c in each of the eight devices. the 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). note . the matching address is always going to be a location 0 in a four-entry page for 272-bit search (two lsbs of the matching index will be 00). the search command is a pipelined operation and executes search at one fourth the rate of the frequency of clk2x for 272-bit searches in x272-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-29 . the latency of search from command to sram access cycle is 5 for only a single device in the table and tlsz = 01. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-30 . 10.14 272-bit search on tables configured as 272 using up to 31 cynse70064 devices the hardware diagram of the search subsystem of 31 devices is shown in figure 10-57 . each of the four blocks in the diagram represents a block of eight cynse70064 devices, except the last which has seven devices.the diagram for a block of eight devices is shown in figure 10-58 . the following are the parameters programmed into the 31 devices. table 10-29. the latency of search from c and d cycles to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 8k 272 bits 4 1 ? 8 (tlsz = 01) 64k 272 bits 5 1 ? 31 (tlsz = 10) 248k 272 bits 6 table 10-30. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 figure 10-56. 272 table with eight devices cfg = 10101010 271 0 location 0 4 8 12 262140 (272-bit configuration) address k gmr 271 0 (first matching entry) l a b 01 c d 23 must be same in each of the eight devices
cynse70064 document #: 38-02041 rev. ** page 79 of 124 first thirty devices (devices 0 ? 29): cfg = 10101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 10101010, tlsz = 10, hlat = 000, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-31 . for the purpose of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. figure 10-59 shows the timing diagram for a search command in the 272-bit-configured table consisting of 31 devices for each of the eight devices in block number 0. figure 10-60 shows the timing diagram for a search command in the 272-bit-configured table of 31 devices for all devices above the winning device in block number 1. figure 10-61 shows the timing diagram for the globally winning device (the final winner within its own and all blocks) in block number 1. figure 10-62 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-63 , figure 10-64 , and figure 10-65 , respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winn ing device for block number 2. figure 10-66 , figure 10-67 , figure 10-68 , and figure 10-69 , respectively, show the timing diagrams of the device above the globally winning device, the globally winning device, the devices below the globally winning device (ex cept device 30), and last device (device 30) for block number 3. the 272-bit search operation is pipelined and executes as follows. four cycles from the last cycle of the search command each of the devices knows the outcome internal to it for that operation. in the fifth cycle from the search command, the devices in a block (which is less than or equal to eight devices resolving the winner within them using an lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner. in the sixth cycle after the search command, the blocks of devices resolve the winning block through a bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the winning block is the global winning device for the search operation. table 10-31. hit/miss assumption search number 1 2 3 block 0 miss miss miss block 1 miss miss hit block 2 miss hit hit block 3 hit hit miss
cynse70064 document #: 38-02041 rev. ** page 80 of 124 bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24 ? 30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 10-57. hardware diagram for a table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 81 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] bhi[2:0] ssv, ssf figure 10-58. hardware diagram for a block of up to eight devices
cynse70064 document #: 38-02041 rev. ** page 82 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (misson this device.) search3 (misson this device.) |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 figure 10-59. timing diagram for each device in block number 0 (miss on each device)
cynse70064 document #: 38-02041 rev. ** page 83 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) figure 10-60. timing diagram for each device above the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 84 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 0 1 1 1 (miss on this device.) (miss on this device.) figure 10-61. timing diagram for globally winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 85 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 (miss on this device.) (miss on this device.) (miss on this device.) figure 10-62. timing diagram for devices below the winning device in block number 1
cynse70064 document #: 38-02041 rev. ** page 86 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 (miss on this device; hit in block 0 or 1.) |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) figure 10-63. timing diagram for devices above the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 87 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (global winner.) i(bhi[2:0]) 0 search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 1 1 1 z z z z z z cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 z z z (miss on this device.) figure 10-64. timing diagram for globally winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 88 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) figure 10-65. timing diagram for devices below the winning device in block number 2
cynse70064 document #: 38-02041 rev. ** page 89 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) figure 10-66. timing diagram for devices above the winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 90 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (hit but not global winner.) i(bhi[2:0]) 0 (global winner.) search3 |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 1 1 1 z z z z z cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 z (miss on this device.) figure 10-67. timing diagram for globally winning device in block number 3
cynse70064 document #: 38-02041 rev. ** page 91 of 124 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) figure 10-68. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)
cynse70064 document #: 38-02041 rev. ** page 92 of 124 the following is the sequence of operation for a single 272-bit search command (also refer to subsection 10.2, ? commands and command parameters ? on page 19). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched. dq[67:0] must be driven with the 68-bit data ([271:204])to be compared to all locations 0 in the four 68-bits-word page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a 272-bit search. cmd[8:7] is ignored in this cycle. cycle b : the host asic continues to drive the cmdv high and applies search command (10) on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([203:136]) to be compared to all locations 1 in the four 68-bits-word page. cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for the bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven by this device on sadr[21:20] if it has a hit. dq[67:0] must be driven with th e 68-bit data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logi c 0. cycle d : the host asic continues to drive the cmdv high and continues to apply search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for a description of ssr[0:7]). the dq[67:0] is driven with the 68-bit data ([67:0]) to be compared t o all locations 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 tabl es. note . for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles c and d. cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 10101010, hlat = 000, tlsz = 10, lram = 1, ldev = 1. note: |(bhi[2:0]) stands for the boolean ? or ? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ? or ? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[21:0] ssf ssv ale_l search1 search2 z 0 0 |(lhi[6:0)] i(bhi[2:0]) 0 (hit on some device above.) search3 0 bho[2:0] 0 z 0 1 cmdv cmd[1:0] cmd[8:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 lho[1:0] 0 z z 0 0 0 z 0 z 1 1 z z 0 z 0 0 z 0 z 0 0 z (hit on some device above.) (hit on some device above.) figure 10-69. timing diagram of the last device in block number 3 (device 30 in the table)
cynse70064 document #: 38-02041 rev. ** page 93 of 124 the logical 272-bit search operation is as shown in figure 10-70 . the entire table of 272-bit entries is compared to a 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command ? s cycles a and c in each of the 31 devices. the 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry ? s location address l is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see ? sram addressing ? on page 101). note . the matching address is always going to be location 0 in a four-entry page for 272-bit search (two lsbs of the matching index will be 00). the search command is a pipelined operation and executes a search at one-fourth the rate of the frequency of clk2x for 272-bit searches in 272-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-32 . the latency of a search from command to sram access cycle is 6 for only a single device in the table and tlsz = 10. in addition , ssv and ssf shift further to the right for different values of hlat, as specified in table 10-33 . 10.15 mixed-sized searches on tables configured with different widths using an cynse70064 device this subsection will cover mixed searches ( 68, 136, and 272) with tables of different widths ( 68, 136, 272). the sample operation shown is for a single device with cfg = 10010000 containing three tables of 68, 136, and 272 widths. the operation can be generalized to a block of eight to 31 devices using four blocks; the timing and the pipeline operation is the same as described previously for fixed searches on a table of one-width-size. figure 10-71 shows three sequential searches: first, a 68-bit search on the table configured as 68, then a 136-bit search on a table configured as 136, and finally a 272-bit search on the table configured as 272 bits that each results in a hit. note .the table 10-32. the latency of search from c and d cycles to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 8k 272 bits 4 1 ? 8 (tlsz = 01) 64k 272 bits 5 1 ? 31 (tlsz = 10) 248k 272 bits 6 table 10-33. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 10101010 271 0 location 0 4 8 12 1015804 (272-bit configuration) address k gmr 271 0 (first matching entry) l a b 01 c d 23 must be same in each of the 31 devices figure 10-70. 272 table with 31 devices
cynse70064 document #: 38-02041 rev. ** page 94 of 124 dq[67:66] will be 00 in each of the two a and b cycles of the 68-bit search (search1). dq[67:66] is 01 in each of the a and b cycles of the 136-bit search (search2). dq[67:66] is 10 in each of the a, b, c, and d cycles of the 272-bit search (search3). by having table designation bits, the cynse70064 enables the creation of many tables in a bank of search engines of different widths. figure 10-72 shows the sample table. two bits in each 68-bit entry will need to designated as the table number bits. one example choice can be the 00 values for the table configured as 68, 01 values for tables configured as 136, and 10 values for tables configured as 272. for the above explanation, it is further assumed that bits [67:66] for each entry will be designed as such table designation bits. cycle clk2x cmdv cmd[1:0] ce_l oe_l hit hit cmd[8:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 1010101010101010, hlat = 010, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[21:0] ssf ssv ale_l search1search2 a2 01 01 search1 search3 a b a b a b a b 0 1 0 10 0 1 1 0 1 0 ab a b a b c d dq d1 d3 cmd[2] 101 1 0 1 a3 search2 01 d2 1 1 0 0 0 0 1 0 1 68 136 hit search2 272 a1 a3 figure 10-71. timing diagram for mixed search (one device) 2 k 16 k 68 4 k 136 272 cfg = 10010000 figure 10-72. multiwidth configurations example
cynse70064 document #: 38-02041 rev. ** page 95 of 124 10.16 lram and ldev description when search engines are cascaded using multiple cynse70064s, the sadr, ce_l, and we_l (three-state signals) are all tied together. in order to eliminate external pull-ups and pull-downs, one device in a bank is designated as the default driver. for non-search or non-learn cycles (see subsection 10.17, ? learn command ? on page 95) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lram bit set. it is important that only one device in a bank of search engines that are cascaded have this bit set. failure to do so will cause contention on sadr, ce_l, and we_l and can potentially cause damage to the device(s). similarly, when search engines using multiple cynse70064s are cascaded, ssf and ssv (also three-state signals) are tied together. in order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. for nonsearch cycles or search cycles with a global miss the ssf and ssv signals are driven by the device with the ldev bit set. it is important that only one device in a bank of search engines that are cascaded together have this bit set. failure to do so will cause contention on ssv and ssf and can potentially cause damage to the device(s). 10.17 learn command bit[0] of each 68-bit data location specifies whether an entry in the database is occupied. if all the entries in a device are occupied, the device asserts fulo signal to inform the downstream devices that it is full. the result of this communication between depth-cascaded devices determines the global full signal for the entire table. the full signal in the last device determines the fullness of the depth-cascaded table. the device contains 16 pairs of internal, 68-bit-wide comparand registers that store the comparands as the device executes searches. on a miss by the search signalled to asic through the ssv and ssf signals (ssv = 1, ssf = 0), the host asic can apply the learn command to learn the entry from a comparand register to the next-free location (see subsection 7.8, ? nfa register ? on page 16). the nfa updates to the next-free location following each write or learn command. in a depth-cascaded table, only a single device will learn the entry through the application of a learn instruction. the determ ination of which device is going to learn is based on the fuli and fulo signalling between the devices. the first non-full device learn s the entry by storing the contents of the specified comparand registers to the location(s) pointed to by nfa. in a 68-configured table the learn command writes a single 68-bit location. in a 136-configured table the learn command writes the next even and odd 68-bit locations. in 136-bit mode, bit[0] of the even and odd 68-bit locations is 0, which indicat es that they are cascaded empty, or 1, which indicates that they are occupied. the global full signal indicates to the table controller (the host asic) that all entries within a block are occupied and that no more entries can be learned. the cynse70064 updates the signal after each write or learn command to a data array. the learn command generates a write cycle to the external sram, also using the nfa register as part of the sram address (see section 12.0, ? sram addressing ? on page 101). the learn command is supported on a single block containing up to eight devices if the table is configured either as a 68 or a 136. the learn command is not supported for 272-configured tables. learn is a pipelined operation and lasts for two clk cycles, as shown in figure 10-73 where tlsz = 00, and figure 10-74 and figure 10-75 where tlsz = 01. figure 10-74 and figure 10-75 assume that the device performing the learn operation is not the last device in the table and has its lram bit set to 0. note . the oe_l for the device with the lram bit set goes high for two cycles for each learn (one during the sram write cycle, and one the cycle before). the latency of the sram write cycle from the second cycle of the instruction is shown in table 10-34 .
cynse70064 document #: 38-02041 rev. ** page 96 of 124 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[21:0] cmd[8:2] x we_l oe_l a1 a2 x xxx x tlsz = 00, lram = 1, ldev = 1. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z z z z 0 0 0 0 0 0 0 ssv ssf 1 0 1 1 ce_l figure 10-73. timing diagram of learn (tlsz = 00)
cynse70064 document #: 38-02041 rev. ** page 97 of 124 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[21:0] ce_l cmd[8:2] x we_l oe_l a1 a2 x xxx x tlsz = 01, lram = 0, ldev = 0. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l z z z z z z z 0 0 z z ssv ssf z 0 0 figure 10-74. timing diagram of learn (except on the last device [tlsz = 01])
cynse70064 document #: 38-02041 rev. ** page 98 of 124 the learn operation lasts two clk cycles. the sequence of operation is as follows. cycle 1a : the host asic applies the learn instruction on cmd[1:0] using cmdv = 1. the cmd[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 136-bit-configured table. for a learn in a 68-bit-configured table, the even-numbered comparand specified by this index will be written. cmd[8:7] carries the bits that will be driven on sadr[21:20] in the sram write cycle. cycle 1b : the host asic continues to drive the cmdv to 1, the cmd[1:0] to 11, and the cmd[5:2] with the comparand pair index. cmd[6] must be set to 0 if the learn is being performed on a 68-bit-configured table, and to 1 if the learn is being performed on a 136-bit-configured table. cycle 2 : the host asic drives the cmdv to 0. at the end of cycle 2, a new instruction can begin. the latency of the sram write is the same as the search to the sram read cycle. it is measured from the second cycle of the learn instruction. table 10-34. the latency of sram write cycle from second cycle of learn instruction number of devices latency in clk cycles 1 (tlsz = 00) 4 1 ? 8 (tlsz = 01) 5 1 ? 31 (tlsz = 10) 6 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[21:0] ce_l cmd[8:2] x we_l oe_l x xxx x tlsz = 01, lram = 1, ldev = 1. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z z z z 0 zz zz 0 0 ssv ssf 1 1 1 0 z 1 1 figure 10-75. timing diagram of learn on device number 7 (tlsz = 01)
cynse70064 document #: 38-02041 rev. ** page 99 of 124 11.0 depth-cascading the search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 2 72 bits). the devices perform all the necessary arbitration to decide which device will drive the sram bus. the latency of the searches increases as the table size increases; the search rate remains constant. 11.1 depth-cascading up to eight devices (one block) figure 11-1 shows how up to eight devices can be cascaded to form 256k 68, 128k 136, or 64k 272 tables. it also shows the interconnection between the devices for depth-cascading. each search engine asserts the lho[1] and lho[0] signals to inform downstream devices of its result. the lhi[6:0] signals for a device are connected to lho signals of the upstream devices . the host asic must program the tlsz to 01 for each of up to eight devices in a block. only a single device drives the sram bus in any single cycle. lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 11-1. depth-cascading to form a single block
cynse70064 document #: 38-02041 rev. ** page 100 of 124 11.2 depth-cascading up to 31 devices (four blocks) figure 11-2 shows how to cascade up to four blocks. each block contains up to eight cynse70064 devices except the last, and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block. note . the interconnection between blocks for depth-cascading is important. for each search, a block asserts bho[2], bho[1], and bho[0]. the bho[2:0] signals for a block are the signals taken only from the last device in the block. for all other devices wi thin that block, these signals stay open and floating. the host asic must program the table size (tlsz) field to 10 in each of the devices for cascading up to 31 devices (in up to four blocks). 11.3 depth-cascading for a full signal bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). for each learn or pio write to t he data array, each device asserts fulo[1] and fulo[0] if it does not have any empty locations within it (see figure 11-3 ). each device combines the fulo signals from the devices above it with its own full status to generate a full signal that gives the fu ll status of the table up to the device asserting the full signal. figure 11-3 shows the hardware connection diagram for generating the full signal that goes back to the asic. in a depth-cascaded block of up to eight devices, the full signal from the last dev ice should be fed back to the asic controller to indicate the fullness of the table. the full signal of the other devices should be left open. note . the learn instruction is supported for only up to eight devices, whereas full cascading is allowed only for one block in tables containing more than eight devices. in tables for which a learn instruction is not going to be used, the bit[0] of eac h 68-bit entry should always be set to 1. bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24-30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 11-2. depth-cascading four blocks
cynse70064 document #: 38-02041 rev. ** page 101 of 124 12.0 sram addressing table 12-1 describes the commands used to generate addresses on the sram address bus. the index [14:0] field contains the address of a 68-bit entry that results in a hit in 68-bit-configured partition. it is the address of the 68-bit entry that lies at the 136-bit page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively. section 7.0, ? registers ? on page 13 of this specification, describes the nfa and ssr registers. adr[14:0] contains the address supplied on the dq bus during pio access to the cynse70064. command bits 8, and 7 {cmd[8:7]} are passed from the command to the sram address bus. see section 10.0, ? commands ? on page 18, for more information. id[4:0] is the id of the device driving the sram bus (see section 17.0, ? pinout descriptions and package diagrams ? on page 122, for more information). fulo[0] 654 3210 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[1] 654 3 210 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[0] 6543210 fuli fulo[0] 65 4 321 0 fuli 6 5 4 3210 fuli 65 4 3210 fulo[0] fuli fuli fuli fulo[1] fulo[1] fulo[1] dq[67:0] fulo[1] fulo[0] v ddq v ddq v ddq v ddq v ddq v ddq full full full full full full full full v ddq cynse70064 cynse70064 cynse70064 cynse70064 cynse70064 cynse70064 cynse70064 cynse70064 fuli fulo[0] figure 11-3. full generation in a cascaded table
cynse70064 document #: 38-02041 rev. ** page 102 of 124 12.1 generating an sram bus address 12.2 sram pio access the remainder of section 12.0 describes sram read and sram write operations. sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will be depend on the value programmed for the tlsz parameter in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruction to the sram address plus the hlat programmed in the configu- ration register. note . sram read is a blocking operation ? no new instruction can begin until the ack is returned by the selected device performing the access. sram write enables write access to the off-chip sram containing associative data. the latency from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter programmed in the device configuration register. note . sram write is a pipelined operation ? new instruction can begin right after the previous command has ended. 12.3 sram read with a table of one device sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter programmed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruction to the sram address plus the hlat programmed in the configuration register. the following explains the sram read operation in a table with only one device that has the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 12-1 shows the associated timing diagram. for the following description, the selected device refers to the only device in the table because it is the only device to be accessed. cycle 1a : the host asic applies the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[21:20] on cmd[8:7]. cycle 1b : the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. cycle 2 : the host asic floats dq[67:0] to a three-state condition. cycle 3 : the host asic keeps dq[67:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[67:0] and drives ack from high-z to low. cycle 5 : the selected device drives the read address on sadr[21:0]; it also drives ack high, ce_l low, and ale_l low. cycle 6 : the selected device drives ce_l high, ale_l high, the sadr bus, the dq bus in a three-state condition, and ack low. at the end of cycle 6, the selected device floats ack in a three-state condition, and a new command can begin. table 12-1. sram bus address command sram operation 21 20 [19:15] [14:0] search read c8 c7 id[4:0] index[14:0] learn write c8 c7 id[4:0] nfa[14:0] pio read read c8 c7 id[4:0] adr14:0] pio write write c8 c7 id[4:0] adr[14:0] indirect access write/read c8 c7 id[4:0] ssr[14:0]
cynse70064 document #: 38-02041 rev. ** page 103 of 124 12.4 sram read with a table of up to eight devices the following explains the sram read operation completed through a table of up to eight devices using the following parameters: tlsz = 01. figure 12-2 diagrams a block of eight devices. the following assumes that sram access is successfully achieved through cynse70064 device number 0. figure 12-3 and figure 12-4 show timing diagrams for device number 0 and device number 7, respectively. cycle 1a : the host asic applies the read instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which id[4:0] matches the dq[25:21] lines. during this cycle the host asic also supplies sadr[21:20] on cmd[8:7]. cycle 1b : the host asic continues to apply the read instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10 to select the sram address. cycle 2 : the host asic floats dq[67:0] to a three-state condition. cycle 3 : the host asic keeps dq[67:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[67:0]. cycle 5 : the selected device continues to drive dq[67:0] and drives ack from high-z to low. cycle 6 : the selected device drives the read address on sadr[21:0]. it also drives ack high, ce_l low, we_l high, and ale_l low. cycle 7 : the selected device drives ce_l , ale_l, we_l, and dq bus in a three-state condition. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in three-state condition and a new command can begin. cycle clk2x dq read address ack oe_l we_l ale_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00, hlat = 000, lram = 1, ldev = 1 phs_l cmd[8:2] a b z z 0 1 0 z z 0 0 1 z 1 z 1 ssv 0 0 ssf ce_l 1 0 1 dq driven by cynse70064 cmdv cmd[1:0] figure 12-1. sram read access (tlsz = 00, hlat = 000, lram = 1, ldev = 1)
cynse70064 document #: 38-02041 rev. ** page 104 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 12-2. table of a block of eight devices
cynse70064 document #: 38-02041 rev. ** page 105 of 124 cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 0, ldev = 0. phs_l cmd[8:2] a b z z z z 0 z z z ssv z ssf ale_l z 0 z z 0 0 1 z z 1 cycle 7 dq driven by selected cynse70064. figure 12-3. sram read through device number 0 in a block of eight devices
cynse70064 document #: 38-02041 rev. ** page 106 of 124 12.5 sram read with a table of up to 31 devices the following explains the sram read operation accomplished through a table of up to 31 devices, using the following param- eters: tlsz = 10. the diagram of such a table is shown in figure 12-5 . the following assumes that sram access is being accomplished through cynse70064 device number 0, that device number 0 is the selected device. figure 12-6 and figure 12-7 show the timing diagrams for device number 0 and device number 30, respectively. cycle 1a : the host asic applies the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[21:20] on cmd[8:7]. cycle 1b : the host asic continues to apply the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. cycle 2 : the host asic floats dq[67:0] to a three-state condition. cycle 3 : the host asic keeps dq[67:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[67:0]. cycles 5 to 6 : the selected device continues to drive dq[67:0]. cycle 7 : the selected device continues to drive dq[67:0] and drives an sram read cycle. cycle 8 : the selected device drives acl from z to low. cycle 9 : the selected device drives ack to high. cycle 10 : the selected device drives ack from high to low. at the end of cycle 10, the selected device floats acl in a three-state condition. cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 1, ldev = 1. phs_l cmd[8:2] a b z 0 1 z z 1 1 ssv z ssf ale_l 1 z 1 z z z ack z 1 figure 12-4. sram read timing for device number 7 in a block of eight devices
cynse70064 document #: 38-02041 rev. ** page 107 of 124 bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24 ? 30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 12-5. table of 31 devices made of four blocks
cynse70064 document #: 38-02041 rev. ** page 108 of 124 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv z z z z cmdv cmd[1:0] cmd[8:2] 00 read a b address dq address 0 z z 1 we_l oe_l z ale_l z 0 z z z z z 1 0 0 ack dq driven by the selected cynse70064 tlsz = 10, hlat = 010, lram = 0, ldev =0 figure 12-6. sram read through device number 0 in a bank of 31 devices (device number 0 timing)
cynse70064 document #: 38-02041 rev. ** page 109 of 124 12.6 sram write with a table of one device sram write enables write access to the off-chip sram that contains associative data. the latency from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction, and will depen d on the tlsz value parameter programmed in the device configuration register. the following explains the sram write operation accomplished through a table of only one device with the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 12-8 shows the timing diagram. for the following description the selected device refers to the only device in the table as it is the only device that will be accessed. cycle 1a : the host asic applies the write instruction on the cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[21:20] on cmd[8:7] in this cycle. note . cmd[2] must be set to 0 for sram write as burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on the cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note that cmd[2] must be set to 0 for sram write as burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. cycle 3 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. at the end of cycle 3, a new command can begin. the write is a pipelined operation, however the write cycle appears at the sram bus with the same latency as the latency of search instruction as measured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[8:2] 00 read a b address dq z 1 we_l oe_l 0 ale_l 1 z 1 z ack z 1 1 z tlsz = 10, hlat = 010, lram = 1, ldev = 1 figure 12-7. sram read through device number 0 in bank of 31 devices (device number 30 timing)
cynse70064 document #: 38-02041 rev. ** page 110 of 124 12.7 sram write with a table of up to eight devices the following explains the sram write operation done through a table(s) of up to eight devices with the following parameters (tlsz = 01). the diagram of such a table is shown in figure 12-9 . the following assumes that sram access is done through cynse70064 device number 0. figure 12-10 and figure 12-11 show the timing diagram for device number 0 and device number 7, respectively. cycle 1a : the host asic applies the write instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[21:20] on cmd[8:7] in this cycle. note . cmd[2] must be set to 0 for sram write, as burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write, as burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. cycle 3 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. at the end of cycle 3, a new command can begin. the write is a pipelined operation, but the write cycle appears at the sram bus with the same latency as that of a search instruction as measured from the second cycle of the write command. cycle clk2x cmdv cmd[1:0] dq write address ack oe_l we_l ale_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00, hlat = 000, lram = 1, ldev = 1. phs_l cmd[8:2] a b x 0 1 z z 1 ssv 0 0 ssf ce_l 1 x x 1 0 0 0 figure 12-8. sram write access (tlsz = 00, hlat = 000, lram = 1, ldev = 1)
cynse70064 document #: 38-02041 rev. ** page 111 of 124 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[67:0] sram lho[1] lho[0] cynse70064 #0 cynse70064 #1 cynse70064 #2 cynse70064 #3 cynse70064 #4 cynse70064 #5 cynse70064 #6 cynse70064 #7 4 bho[2] bho[2] cmdv cmd[8:0] ssf, ssv figure 12-9. table of a block of eight devices
cynse70064 document #: 38-02041 rev. ** page 112 of 124 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv z z z cmdv cmd[1:0] cmd[8:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z tlsz = 01, hlat = xxx, lram = 0, ldev = 0 figure 12-10. sram write through device number 0 in a block of eight devices
cynse70064 document #: 38-02041 rev. ** page 113 of 124 12.8 sram write with table(s) of up to 31 devices the following explains the sram write operation done through a table(s) of up to 31 devices with the following parameters (tlsz = 10). the diagram of such table(s) is shown in figure 12-12 . the following assumes that sram access is done through cynse70064 device number 0 ? device 0 is the selected device. figure 12-13 and figure 12-14 show the timing diagram for device number 0 and device number 30, respectively. cycle 1a : the host asic applies the write instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[21:20] on cmd[8:7] in this cycle. note . cmd[2] must be set to 0 for sram write, as burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write, as burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. cycle 3 : the host asic continues to drive dq[67:0]. the data in this cycle is not used by the cynse70064. at the end of cycle 3, a new command can begin. the write is a pipelined operation, but the write cycle appears at the sram bus with the same latency as that of a search instruction, as measured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[8:2] 01 write a b address dq z we_l oe_l 0 ale_l z z ack x x 1 0 1 1 z 1 1 z 1 tlsz = 01, hlat = xxx, lram = 1, ldev = 1 figure 12-11. sram write timing for device number 7 in block of eight devices
cynse70064 document #: 38-02041 rev. ** page 114 of 124 bho[2] block of 8 cynse70064s block 0 (devices 0 ? 7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70064s block 3 (devices 24 ? 30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70064s block 1 (devices 8 ? 15) block of 8 cynse70064s block 2 (devices 16 ? 23) dq[67:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[8:0], cmdv ssf, ssv figure 12-12. table of 31 devices (four blocks)
cynse70064 document #: 38-02041 rev. ** page 115 of 124 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv z z z cmdv cmd[1:0] cmd[8:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z tlsz = 10, hlat = xxx, lram = 0, ldev = 0 figure 12-13. sram write through device number 0 in bank of 31 devices (device 0 timing)
cynse70064 document #: 38-02041 rev. ** page 116 of 124 13.0 application figure 13-1 shows how a search engine subsystem can be formed using a host asic and an cynse70064 bank. it also shows how this search engine subsystem is integrated in a switch or router. the cynse70064 can access synchronous and asynchronous srams by allowing the host asic to set the same hlat parameter in all search engines within a bank of search engines. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[21:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[8:2] 01 write a b address dq z we_l oe_l 0 ale_l z z ack x x 1 1 1 z 1 1 z 1 tlsz = 10, hlat = xxx, lram = 1, ldev = 1 figure 12-14. sram write through device number 0 in bank of 31 cynse70064 devices (device number 30 timing)
cynse70064 document #: 38-02041 rev. ** page 117 of 124 14.0 jtag (1149.1) testing the cynse70064 supports the test access port and boundary scan architecture as specified in the ieee jtag standard number 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 14-1 describes the operations that the test access port controller supports, and table 14-2 describes the tap device id register. note . to disable jtag functionality, connect the tck, tms and tdi pins to v ddq through a pull-up, and trst_l to ground through a pull-down. table 14-1. supported operations instruction type description sample/preload mandatory sample/preload . this operation loads the values of signals going to and from i/o pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test . this operation uses boundary scan values shifted in from tap to test connectivity external to the device. intest optional internal test . this operation allows slow-speed functional testing of the device using the boundary scan register to provide i/o values. table 14-2. tap device id register field range initial value description revision [31:28] 0001 revision number . this is the current device revision number. numbers start from 1 and increment by 1 for each revision of the device. part number [27:12] 0000 0000 0000 0001 this is the part number for the device. mfid [11:1] 000_1101_1100 manufacturer id . this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit. p r o g r a m m e m o r y n e t w o r k l i n e i n t e r f a c e s s y s t e m b u s n e t w o r k p r o c e s s o r s w i t c h f a b r i c h o s t a s i c s e a r c h e n g i n e s r a m b a n k figure 13-1. sample switch/router using the cynse70064 device
cynse70064 document #: 38-02041 rev. ** page 118 of 124 15.0 electrical specifications this section describes the electrical specifications, capacitance, operating conditions, dc characteristics, and ac timing para m- eters for the cynse70064, as shown in table 15-1 and table 15-2 . table 15-1. dc electrical characteristics for cynse70064 parame- ter description test conditions min. max. unit i li input leakage current v ddq = v ddq max, v in = 0 to v ddq max ? 10 10 a i lo output leakage current v ddq = v ddq max, v in =0 to v ddq max ? 10 10 a v il input low voltage (v ddq = 3.3v) ? 0.3 0.8 v v ih input high voltage (v ddq = 3.3v) 2.0 v ddq + 0.3 v v ol output low voltage (v ddq = 3.3v) v ddq = v ddq min, i ol = 8ma 0.4 v v oh output high voltage (v ddq = 3.3v) v ddq = v ddq min, i oh = 8ma 2.4 v v il input low voltage (v ddq = 2.5v) ? 0.3 0.7 v v ih input high voltage (v ddq = 2.5v) 1.7 v ddq + 0.3 v v ol output low voltage (v ddq = 2.5v) v ddq = v ddq min, i ol = 8ma 0.4 v v oh output high voltage (v ddq = 2.5v) v ddq = v ddq min, i oh = 8ma 2.0 v i dd2 3.3v supply current at v dd max 66 mhz search rate, l out =0ma 200 ma i dd2 3.3v supply current at v dd max 50 mhz search rate, l out = 0ma 150 ma i dd2 2.5v supply current at v dd max 66 mhz search rate, l out =0ma 160 ma i dd2 2.5v supply current at v dd max 50 mhz search rate, l out = 0ma 120 ma i ddl 1.8v supply current at v dd max 66 mhz search rate 2300 ma i ddl 1.8v supply current at v dd max 50 mhz search rate 1800 ma symbol parameter max unit c in input capacitance 6 pf [8] c out output capacitance 6 pf [9] table 15-2. operating conditions for cynse70064 symbol parameter min (3.3v) max (3.3v) min (2.5v) max (2.5v) unit v ddq operating voltage for io 3.135 3.465 2.4 2.6 v v dd operating supply voltage 1.7 1.9 1.7 1.9 v v ih input high voltage [10] 2.0 v ddq + 0.3 1.7 v ddq + 0.3 v v il input low voltage [11] ? 0.3 0.8 ? 0.3 0.7 v t a ambient operating temperature 0 70 0 70 c supply voltage tolerance ? 5% +5% ? 5% +5% notes: 8. f = 1 mhz, v in = 0 v. 9. f = 1 mhz, v out = 0 v. 10. maximum allowable applies to overshoot only (v ddq is 2.5 v supply). 11. minimum allowable applies to undershoot only.
cynse70064 document #: 38-02041 rev. ** page 119 of 124 16.0 ac timing wave forms table 16-1 shows the ac timing parameters for the cynse70064 device; table 16-2 shows the same parameters but for 2.5v. table 16-1. ac timing parameters with clk2x parameter description CYNSE70064-050 cynse70064-066 unit min. max. min. max. f clock clk2x frequency. 100 133 mhz t clk clk2x period. 10 7.5 ns t ckhi clk2x high pulse. [12] 4.0 3.0 ns t cklo clk2x low pulse. [12] 4.0 3.0 ns t isch input setup time to clk2x rising edge. [12] 2.5 2.5 ns t ihch input hold time to clk2x rising edge. [12] 0.6 0.6 ns t icsch cascaded input setup time to clk2x rising edge. [12] 4.2 4.2 ns t ichch cascaded input hold time to clk2x rising edge. [12] 0.6 0.6 ns t ckhov rising edge of clk2x to lho, fulo, bho, full valid. [13] 9.5 8.5 ns t ckhdv rising edge of clk2x to dq valid. [13] 10.0 9.0 ns t ckhdz rising edge of clk2x to dq high-z. [14] 1.2 9.5 1.2 8.5 ns t ckhsv rising edge of clk2x to sram bus valid. [13] 10.0 9.0 ns t ckhshz rising edge of clk2x to sram bus high-z. [14] 7.0 6.5 ns t ckhslz rising edge of clk2x to sram bus low-z. [14] 7.5 7.0 ns table 16-2. 2.5v ac table for test condition of cynse70064 conditions results input pulse levels (v ddq = 3.3v) gnd to 3.0v input pulse levels (v ddq = 2.5v) gnd to 2.5v input rise and fall times measured at 0.3v and 2.7v (v ddq = 3.3v) 2 ns see ( figure 16-1 ) input rise and fall times measured at 0.25v and 2.25v (v ddq = 2.5v) 2 ns see ( figure 16-1 ) input timing reference levels (v ddq = 3.3v) 1.5v input timing reference levels (v ddq = 2.5v) 1.25 output reference levels (v ddq = 3.3v) 1.5v output reference levels (v ddq = 2.5v) 1.25v output load see figure 16-2 and figure 16-3 notes: 12. values are based on 50% signal levels. 13. based on an ac load of cl = 30pf (see figure 16-1 , figure 16-2 , and figure 16-3 ). 14. these parameters are sampled but not 100% tested, and are based on an ac load of 5pf. 10% 90% 90% 10% gnd +2.5 v ddq = 2.5v / +3.0v v ddq = 3.3v figure 16-1. input wave form for cynse70064
cynse70064 document #: 38-02041 rev. ** page 120 of 124 figure 16-4 shows timing waveform diagrams. notes: 15. output loading is specified with c l =5 pf as in figure 16-3 . transition is measured at 200 mv from steady-state voltage. 16. the load used for v oh , v ol testing is shown in figure 16-3 . v l = 1.25v for v ccio = 2.5v v l = 1.5v for v ccio = 3.3v d out c = 30 pf ac load z0 = 50 ? 50 ? figure 16-2. output load for cynse70064 5 pf 208 ? (2.5v) 158 ? (3.3v) q +2.5 v or +3.3v for high-z and v ol /v oh 1,2 192 ? (2.5v) 175 ? (3.3v) figure 16-3. 2.5 i/o output load equivalent for cynse70064
cynse70064 document #: 38-02041 rev. ** page 121 of 124 clk signal signal signal signal signal group 0 group 2 group 3 group 5 group 4 0 t ihch t isch t icsch t ihch signal group 0: phs_l, rst_l. signal group 1: dq, cmd, cmdv. signal group 2: lhi, bhi, fuli. signal group 3: lho, bho, fulo, full. signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv. signal group 5: dq, ack, eot. t ckhov t ckhov t ckhdz t ckhdv t ckhshz t ckhslz t ckhsv cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle clk2x signal group 1 t ihch t isch t ihch t isch t ichch figure 16-4. ac timing wave forms with clk2x
cynse70064 document #: 38-02041 rev. ** page 122 of 124 17.0 pinout descriptions and package diagrams in the following figures and tables the cynse70064 device pinout descriptions and package diagrams are shown. figure 17-1 shows the pinout diagram, table lists descriptions for the pinout diagram, and figure 19-1 illustrates the package from various views. 18.0 ordering information table 18-1 provides ordering information. table 18-1. ordering information part number description frequency temperature range cynse70064 ? 050 search engine 50 mhz commercial cynse70064 ? 066 search engine 66 mhz commercial cynse70064 ? 083 search engine 83 mhz commercial y w v u t r p n m l k j h g f e d c b a y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 nc nc dq64 gnd nc nc nc eot ack nc v dd dq60 v ddq nc v dd nc dq56 dq50 dq52 nc full v ddq gnd v dd fulo1 v ddq nc rstl fuli5 nc nc nc dq62 nc v dd dq66 nc dq54 dq58 v ddq fulo0 gnd dq46 dq48 dq42 v ddq nc dq40 gnd dq44 dq36 v dd nc dq38 fuli4 fuli6 fuli1 fuli2 v ddq fuli3 fuli0 bho0 bho1 bho2 v dd bhi2 v dd bhi1 bhi0 v ddq lho1 lho0 lhi6 lhi5 lhi4 gnd nc lhi3 v ddq lhi1 v dd lhi2 lhio id4 id2 id3 id1 trst_l dq67 v ddq id0 tms tck gnd dq59 dq55 tdo tdi nc dq63 v ddq dq47 nc dq49 nc v dd nc dq61 dq51 dq53 v dd nc nc dq65 dq57 v ddq nc gnd dq45 dq43 dq39 dq41 v dd dq37 dq35 v ddq dq33 dq31 nc v ddq dq29 v dd v ddq nc gnd nc dq23 dq19 dq15 dq25 v ddq dq17 dq27 dq21 dq9 dq11 dq13 v dd dq1 dq5 dq7 nc gnd nc nc v ddq sad5 v ddq nc sad0 v dd dq3 sad7 sad6 sad4 sad3 nc nc sad11 nc v ddq sad2 sad1 nc v dd sad8 nc dq12 dq0 nc dq8 dq18 dq6 v dd v ddq dq16 v ddq dq22 dq14 v dd gnd dq24 dq20 dq28 dq26 nc v ddq dq34 dq30 v ddq dq32 we_l v dd gnd clk2x sad15 gnd v ddq nc gnd dq10 v ddq cmd4 cmd2 oe_l sad18 ale_l sad21 sad16 sad12 sad9 dq4 ssf dq2 v dd cmd3 cmd0 phs_l sad19 v ddq v ddq v ddq nc sad10 nc ssv nc nc cmd1 cmdv nc sad20 ce_l v dd sad17 sad14 sad13 nc cmd7 nc cmd8 v ddq v dd nc top left bottom cmd5 cmd6 nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd right figure 17-1. pinout diagram
cynse70064 document #: 38-02041 rev. ** page 123 of 124 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 19.0 package diagrams associative processing technology tm (apt), cynse70032, cynse70064, and cynse70128, are trademarks of cypress semi- conductor. all product and company names mentioned in this document are the trademarks of their respective holders. 272-lead ball grid array (27 27 2.33 mm) bg272 51-85130 figure 19-1. package
cynse70064 document #: 38-02041 rev. ** page 124 of 124 document title: cynse70064 network search engine document number: 38-02041 rev. ecn no. issue date orig. of change description of change ** 111438 02/21/02 afx new data sheet

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